Kaname Uchikura

According to our database, Kaname Uchikura authored at least 5 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

A Model of Implementable SMT Processor on FPGA.

Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

Towards Reconfigurable Cache Memory for a Multithreaded Processor.

Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

2005

Development of a Thread Scheduler for SMT Processor Architecture.

Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation.

Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

2004

Dynamic Allocation of Physical Register Banks for an SMT Processor.

Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004