Kunihiro Fujiyoshi

According to our database, Kunihiro Fujiyoshi authored at least 39 papers between 1994 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Necessary and Sufficient Condition to Generate Representative Clip for Edge-Constrained Clustering of Layout Pattern Classification Problem.

Kunihiro Fujiyoshi, Tomoya Masutani

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2017

Photo-Diode Array Partitioning Problem for a Rectangular Region.

Kunihiro Fujiyoshi, Takahisa Imano

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

A method for photo-diode array partitioning problem.

Kunihiro Fujiyoshi, Takahisa Imano

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2014

A Method of Analog IC Placement with Common Centroid Constraints.

Keitaro Ue, Kunihiro Fujiyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Average placement method with common centroid constraints for analog IC layout design.

Kunihiro Fujiyoshi, Keitaro Ue

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Adjacent common centroid placement for analog IC layout design.

Kenichiro Murotatsu, Kunihiro Fujiyoshi

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2012

An efficient solution space for floorplan of 3D-LSI.

Hiroshi Tezuka, Kunihiro Fujiyoshi

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

A novel representation for repeated placement.

Kunihiro Fujiyoshi, Keisuke Ishihara, Tan Wei Liang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

On the Number of Rooms in a Rectangular Solid Dissection.

Hidenori Ohta, Toshinori Yamada, Kunihiro Fujiyoshi

J. Inf. Process., 2010

2009

A Tree Based Novel Representation for 3D-Block Packing.

Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation.

Natsumi Hirakawa, Kunihiro Fujiyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection.

Hidenori Ohta, Kunihiro Fujiyoshi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

The O-Sequence: Representation of 3D-Dissection.

Hidenori Ohta, Toshinori Yamada, Chikaaki Kodama, Kunihiro Fujiyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout.

Shinichi Koda, Chikaaki Kodama, Kunihiro Fujiyoshi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A fast algorithm for rectilinear block packing based on selected sequence-pair.

Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda

Integr., 2007

DTS: A Tree Based Representation for 3D-Block Packing.

Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Improved method of cell placement with symmetry constraints for analog IC layout design.

Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi

Proceedings of the 2006 International Symposium on Physical Design, 2006

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.

Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Thermal Driven Module Placement Using Sequence-pair.

Norihide Okada, Chikaaki Kodama, Takashi Sato, Kunihiro Fujiyoshi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge.

Chikaaki Kodama, Kunihiro Fujiyoshi

IEICE Trans. Inf. Syst., 2005

A Graph Based Soft Module Handling in Floorplan.

Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004

A novel encoding method into sequence-pair.

Chikaaki Kodama, Kunihiro Fujiyoshi, Teppei Koga

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair.

Kazuya Wakata, Hiroaki Saito, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata, Chikaaki Kodama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair.

Chikaaki Kodama, Kunihiro Fujiyoshi

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy.

Chikaaki Kodama, Kunihiro Fujiyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An improved method of convex-shaped block packing based on sequence-pair [VLSI layout].

Hiroaki Saito, Kazuya Wakata, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

An efficient decoding method of sequence-pair.

Chikaaki Kodama, Kunihiro Fujiyoshi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000

Arbitrary convex and concave rectilinear block packing usingsequence-pair.

Kunihiro Fujiyoshi, Hiroshi Murata

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Simulated annealing search through general structure floorplans using sequence-pair.

Koji Kiyota, Kunihiro Fujiyoshi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Arbitrary convex and concave rectilinear block packing using sequence-pair.

Kunihiro Fujiyoshi, Hiroshi Murata

Proceedings of the 1999 International Symposium on Physical Design, 1999

1998

Module packing based on the BSG-structure and IC layout applications.

Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

VLSI/PCB placement with obstacles based on sequence pair.

Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Design of minimum and uniform bipartites for optimum connection blocks of FPGA.

Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A mapping from sequence-pair to rectangular dissection.

Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

VLSI module placement based on rectangle-packing by the sequence-pair.

Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Module placement on BSG-structure and IC layout applications.

Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Rectangle-packing-based module placement.

Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Design of Optimum Totally Perfect Connection-Blocks of FPGA.

Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

The Totally-Perfect Bipartite Graph and Its Construction.

Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu

Proceedings of the Algorithms and Computation, 5th International Symposium, 1994