# Yoji Kajitani

According to our database

Collaborative distances:

^{1}, Yoji Kajitani authored at least 61 papers between 1979 and 2016.Collaborative distances:

## Awards

## IEEE Fellow

IEEE Fellow 1992, "For outstanding contributions to graph theory and its application to network theory and computer-aided integrated systems design.".

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2016

Floorplan and Placement.

Encyclopedia of Algorithms, 2016

2013

Escaped Boundary Pins Routing for High-Speed Boards.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Coding the objects in place and route CAD.

Proceedings of the International Symposium on Physical Design, 2013

2011

On routing fixed escaped boundary pins for high speed boards.

Proceedings of the Design, Automation and Test in Europe, 2011

2008

Floorplan and Placement.

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

2007

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.

IEICE Transactions, 2007

2006

The Oct-Touched Tile: A New Architecture for Shape-Based Routing.

IEICE Transactions, 2006

Adaptive Porting of Analog IPs with Reusable Conservative Properties.

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

How does partitioning matter for 3D floorplanning?

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

Equidistance routing in high-speed VLSI layout design.

Integr., 2005

A new approach based on LFF for optimization of dynamic hardware reconfigurations.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fixed-outline floorplanning with constraints through instance augmentation.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Theory of T-junction floorplans in terms of single-sequence.

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A device-level placement with multi-directional convex clustering.

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Space-planning: placement of modules with controlled empty area by single-sequence.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Multi-level placement with circuit schema based clustering in analog IC layouts.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Abstraction and optimization of consistent floorplanning with pillar block constraints.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost.

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Consistent floorplanning with hierarchical superconstraints.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.

Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.

Proceedings of the 2002 Design, 2002

Chip size estimation based on wiring area.

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Consistent floorplanning with super hierarchical constraints.

Proceedings of the 2001 International Symposium on Physical Design, 2001

2000

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Self-reforming routing for stochastic search in VLSI interconnection layout.

Proceedings of ASP-DAC 2000, 2000

1999

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Module packing based on the BSG-structure and IC layout applications.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Approximating Steiner trees in graphs with restricted weights.

Networks, 1998

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules.

Proceedings of the ASP-DAC '98, 1998

Air-Pressure-Model-Based Fast Algorithms for General Floorplan.

Proceedings of the ASP-DAC '98, 1998

1997

Design of minimum and uniform bipartites for optimum connection blocks of FPGA.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Performance and reliability driven clock scheduling of sequential logic circuits.

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

A mapping from sequence-pair to rectangular dissection.

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

VLSI module placement based on rectangle-packing by the sequence-pair.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Module placement on BSG-structure and IC layout applications.

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Detailed-Routability of FPGAs with Extremal Switch-Block Structures.

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Mixed Searching and Proper-Path-Width.

Theor. Comput. Sci., 1995

Rectangle-packing-based module placement.

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Minimal acyclic forbidden minors for the family of graphs with bounded path-width.

Discrete Mathematics, 1994

New Approximation Results on Graph Matching and related Problems.

Proceedings of the Graph-Theoretic Concepts in Computer Science, 1994

Design of Optimum Totally Perfect Connection-Blocks of FPGA.

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

The Totally-Perfect Bipartite Graph and Its Construction.

Proceedings of the Algorithms and Computation, 5th International Symposium, 1994

Channel-driven global routing with consistent placement (extended abstract).

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Generalization of aTheorem on the Parametric Maximum Flow Problem.

Discret. Appl. Math., 1993

Optimal single hop multiple bus networks.

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

The Virtual Dimensions of a Straight Line Embedding of a plane Graph.

Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992

Peel-the-box: a concept of switch-box routing and tractable problems.

Integr., 1992

1988

Minimum augmentation of a tree to a K-edge-connected graph.

Networks, 1988

On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three.

Discrete Mathematics, 1988

Ordering of the elements of a matroid such that its consecutive w elements are independent.

Discrete Mathematics, 1988

1986

The minimum augmentation of a directed tree to a

*k*-edge-connected directed graph.
Networks, 1986

Characterization of partial 3-trees in terms of three structures.

Graphs and Combinatorics, 1986

1984

A matroid generalization of theorems of Lewin and Gallai.

Discret. Appl. Math., 1984

The channel expansion problem in layout design.

Proceedings of the 21st Design Automation Conference, 1984

1983

Order of Channels for Safe Routing and Optimal Compaction of Routing Area.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1983

1979

The minimum width routing of A 2-row 2-layer polycell-layout.

Proceedings of the 16th Design Automation Conference, 1979