L. S. S. Pavan Kumar Chodisetti

According to our database, L. S. S. Pavan Kumar Chodisetti authored at least 12 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 75.47 TOPS/W 4-kb Single-Ended SRAM-Based Compute-in-Memory Architecture Using 16-nm FinFET Technology.

L. S. S. Pavan Kumar Chodisetti, Cheng-Yao Lo, Jeffrey Sean Walling, Yang Yi, Leenendra Chowdary Gunnam, Chua-Chin Wang

J. Signal Process. Syst., June, 2026

A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control.

Chua-Chin Wang, Pradyumna Vellanki, Soumika Majumder, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Lean Karlo Santos Tolentino

J. Circuits Syst. Comput., 2026

2025

A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs.

Chua-Chin Wang, Pradyumna Vellanki, Wei-En Chiu, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Yun-Che Chang, Mitch Ming-Chi Chou

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process.

Chua-Chin Wang, Pradyumna Vellanki, Venkata Naveen Kolakaluri, L. S. S. Pavan Kumar Chodisetti, Lean Karlo Santos Tolentino, Mitch Ming-Chi Chou, Oliver Lexter July Alvarez Jose

IEEE Open J. Circuits Syst., 2025

A 5 V_pp 10-Bit 100MS/s Current-Steering DAC as MZM Drivers of PNN Systems.

L. S. S. Pavan Kumar Chodisetti, Chen-Wei Yen, Pradyumna Vellanki, Yung Hung, Chua-Chin Wang

Proceedings of the International Conference on IC Design and Technology, 2025

A Wide Bandwidth TIA with Low Power Consumption for PNN Prototyping.

L. S. S. Pavan Kumar Chodisetti, Jen-Yu Li, Pradyumna Vellanki, Yung-Jr Hung, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Bo-Hao Liao, Pradyumna Vellanki, Tzung-Je Lee

Microelectron. J., 2024

A single-chip PFM-controlled LED driver with 0.5% illuminance variation.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo

Microelectron. J., 2024

A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki

Integr., 2024

An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process.

Pradyumna Vellanki, Hung-Che Tseng, Ying-Xuan Chen, L. S. S. Pavan Kumar Chodisetti, Chua-Chin Wang

Proceedings of the 21st International SoC Design Conference, 2024

Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET.

Pradyumna Vellanki, Venkata Naveen Kolakaluri, Yun-Che Chang, L. S. S. Pavan Kumar Chodisetti, Mitch Ming-Chi Chou, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024