Pradyumna Vellanki
Orcid: 0009-0000-0768-188X
According to our database1,
Pradyumna Vellanki authored at least 13 papers
between 2024 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control.
J. Circuits Syst. Comput., 2026
2025
A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025
A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR-XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025
A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process.
IEEE Open J. Circuits Syst., 2025
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process.
Integr., 2025
A 10-Bit 100 MS/s V<sub>CM</sub>-Based Switching Analog-to-Digital Converter for PNN Systems.
Proceedings of the International Conference on IC Design and Technology, 2025
A 5 V<sub>pp</sub> 10-Bit 100MS/s Current-Steering DAC as MZM Drivers of PNN Systems.
Proceedings of the International Conference on IC Design and Technology, 2025
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025
2024
Microelectron. J., 2024
Microelectron. J., 2024
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic.
Integr., 2024
An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process.
Proceedings of the 21st International SoC Design Conference, 2024
Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024