Josef Weidendorfer

Orcid: 0000-0001-7159-1432

Affiliations:
  • Technical University Munich, Germany


According to our database1, Josef Weidendorfer authored at least 63 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2023
From reactive to proactive load balancing for task-based parallel applications in distributed memory machines.
Concurr. Comput. Pract. Exp., 2023

Phase-aware System-Side Sampling for HPC.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
Proactive Task Offloading for Load Balancing in Iterative Applications.
Proceedings of the Parallel Processing and Applied Mathematics, 2022

A Profiling-Based Approach to Cache Partitioning of Program Data.
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022

Optimizing Hardware Resource Partitioning and Job Allocations on Modern GPUs under Power Caps.
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

Always-on instrumentation for application introspection in HPC.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021
On the Inevitability of Integrated HPC Systems and How they will Change HPC System Operations.
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

2020
Scheduling across Multiple Applications using Task-Based Programming Models.
Proceedings of the Fourth IEEE/ACM Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware, 2020

2019
The Case for a Common Instrumentation Interface for HPC Codes.
Proceedings of the IEEE/ACM International Workshop on Programming and Performance Visualization Tools, 2019

2018
Foreword by Editors / Workshop Description / TPC List.
Proceedings of the 3rd Workshop on Co-Scheduling of HPC Applications, 2018

A Message-Passing Based Algorithm for k-Terminal Reliability.
Proceedings of the 14th European Dependable Computing Conference, 2018

2017
Enabling Application-Integrated Proactive Fault Tolerance.
Proceedings of the Parallel Computing is Everywhere, 2017

Using LLVM for Optimized Lightweight Binary Re-Writing at Runtime.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

On the Applicability of Virtualization in an Industrial HPC Environment.
Proceedings of the Joined Workshops COSH 2017 and VisorHPC 2017, 2017

Dynamic Co-Scheduling Driven by Main Memory Bandwidth Utilization.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
Simulation Driven Performance Analysis for Software Optimization (Simulationsunterstützte Leistungsanalyse von Programmen)
, 2016

Automatic Co-scheduling Based on Main Memory Bandwidth Usage.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2016

The Case for Binary Rewriting at Runtime for Efficient Implementation of High-Level Programming Models in HPC.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Inclusive Cost Attribution for Cache Use Profiling.
Proceedings of the International Conference on Computational Science 2016, 2016

Detailed Characterization of HPC Applications for Co-Scheduling.
Proceedings of the 1st COSH Workshop on Co-Scheduling of HPC Applications, 2016

Co-Scheduling: Prospects and Challenges.
Proceedings of the Co-Scheduling of HPC Applications [extended versions of all papers from COSH@HiPEAC 2016, 2016

Foreword / Workshop Description.
Proceedings of the 1st COSH Workshop on Co-Scheduling of HPC Applications, 2016

Detailed Application Characterization and Its Use for Effective Co-Scheduling.
Proceedings of the Co-Scheduling of HPC Applications [extended versions of all papers from COSH@HiPEAC 2016, 2016

Viability of Virtual Machines in HPC - A State of the Art Analysis.
Proceedings of the Euro-Par 2016: Parallel Processing Workshops, 2016

2015
Case Study on Co-scheduling for HPC Applications.
Proceedings of the 44th International Conference on Parallel Processing Workshops, 2015

2014
Improving the Kuo-Lu-Yeh Algorithm for Assessing Two-Terminal Reliability.
Proceedings of the 2014 Tenth European Dependable Computing Conference, 2014

A Novel Variable Ordering Heuristic for BDD-based K-Terminal Reliability.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

2013
ParCo 2013 PhD Symposium.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

Expression Tree Evaluation by Dynamic Code Generation - Are Accelerators Up for the Task?
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Real Asynchronous MPI Communication in Hybrid Codes through OpenMP Communication Tasks.
Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems, 2013

Data Transfer Requirement Analysis with Bandwidth Curves.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

2012
Fastsg: A Fast Routines Library for Sparse Grids.
Proceedings of the International Conference on Computational Science, 2012

A Memory-efficient Bounding Algorithm for the Two-terminal Reliability Problem.
Proceedings of the Second Workshop on Quantitative Models for Performance and Dependability, 2012

Invasive computing with iOMP.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

An integrated simulation framework for invasive computing.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

UCHPC 2012: Fifth Workshop on UnConventional High Performance Computing.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

Building Input Adaptive Parallel Applications: A Case Study of Sparse Grid Interpolation.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
Intel Core Microarchitecture, x86 Processor Family.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Sparse matrix operations on several multi-core architectures.
J. Supercomput., 2011

autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems.
Trans. High Perform. Embed. Archit. Compil., 2011

Compact data structure and scalable algorithms for the sparse grid technique.
Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2011

Workload Balancing on Heterogeneous Systems: A Case Study of Sparse Grid Interpolation.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

UCHPC 2011: Fourth Workshop on UnConventional High Performance Computing.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

Performance optimization by dynamic code transformation.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Considering GPGPU for HPC Centers: Is It Worth the Effort?
Proceedings of the Facing the Multicore-Challenge, 2010

UCHPC 2010: Third Workshop on UnConventional High Performance Computing.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Sparse Matrix Operations on Multi-core Architectures.
Proceedings of the Parallel Computing Technologies, 10th International Conference, 2009

Exploiting memory hierarchies in scientific computing.
Proceedings of the 2009 International Conference on High Performance Computing & Simulation, 2009

Parallel MLEM on Multicore Architectures.
Proceedings of the Computational Science, 2009

Argument Controlled Profiling.
Proceedings of the Euro-Par 2009, 2009

2008
Off-loading application controlled data prefetching in numerical codes for multi-core processors.
Int. J. Comput. Sci. Eng., 2008

Sequential Performance Analysis with Callgrind and KCachegrind.
Proceedings of the Tools for High Performance Computing, 2008

2007
Latencies of Conflicting Writes on Contemporary Multicore Architectures.
Proceedings of the Parallel Computing Technologies, 2007

2005
Comprehensive Cache Inspection with Hardware Monitors.
Proceedings of the Parallel Computing Technologies, 2005

Collecting and Exploiting Cache-Reuse Metrics.
Proceedings of the Computational Science, 2005

2004
Cache Optimizations for Iterative Numerical Codes Aware of Hardware Prefetching.
Proceedings of the Applied Parallel Computing, 2004

A Tool Suite for Simulation Based Analysis of Memory Access Behavior.
Proceedings of the Computational Science, 2004

A Data Structure Oriented Monitoring Environment for Fortran OpenMP Programs.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Cache Simulation Based on Runtime Instrumentation for OpenMP Applications.
Proceedings of the Proceedings 37th Annual Simulation Symposium (ANSS-37 2004), 2004

2003
Konzepte zur Optimierung der Skalierbarkeit von parallelen Fahrzeugkollisionsberechnungen und ihre industrielle Realisierbarkeit.
PhD thesis, 2003

2001
A Framework for Transparent Load Balancing in Parallel Numerical Simulation.
Proceedings of the Proceedings 34th Annual Simulation Symposium (SS 2001), 2001

1999
SCI Sockets Library.
Proceedings of the SCI: Scalable Coherent Interface, 1999


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