Laurent Vachez

According to our database, Laurent Vachez authored at least 4 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology.

Piyush Jain, Akshay Kumar, Nicolaas Van Winkelhoff, Didier Gayraud, Surya Gupta, Abdelali El Amraoui, Giorgio Palma, Alexandra Gourio, Laurent Vachez, Luc Palau, Jean-Christophe Buy, Cyrille Dray

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2012

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC^TM eFlash Memories.

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez

J. Electron. Test., 2012

2011

On using a SPICE-like TSTAC™ eFlash model for design and test.

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

A two-layer SPICE model of the ATMEL TSTAC^TM eFlash memory technology for defect injection and faulty behavior prediction.

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez

Proceedings of the 15th European Test Symposium, 2010