Cyrille Dray

According to our database, Cyrille Dray authored at least 8 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Transitioning eMRAM from Pilot Project to Volume Production.

Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim

Proceedings of the IEEE International Test Conference, 2023

2021

A Compact Model for Scalable MTJ Simulation.

Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava, Cyrille Dray

CoRR, 2021

2020

A 14.7Mb/mm² 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference.

El Mehdi Boujamaa, Samsudeen Mohamed Ali, Steve Ngueya Wandji, Alexandra Gourio, Suk-Soo Pyo, Gwanhyeob Koh, Yoonjong Song, Taejoong Song, Jongwook Kye, Jean-Christophe Vial, Andrew Sowden, Manuj Rathor, Cyrille Dray

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

MBIST Supported Multi Step Trim for Reliable eMRAM Sensing.

Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda

Proceedings of the IEEE International Test Conference, 2020

MBIST Support for Reliable eMRAM Sensing.

Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Cyrille Dray, El Mehdi Boujamaa

Proceedings of the IEEE European Test Symposium, 2020

High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology.

Piyush Jain, Akshay Kumar, Nicolaas Van Winkelhoff, Didier Gayraud, Surya Gupta, Abdelali El Amraoui, Giorgio Palma, Alexandra Gourio, Laurent Vachez, Luc Palau, Jean-Christophe Buy, Cyrille Dray

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2017

Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories.

Salmen Mraihi, El Mehdi Boujamaa, Cyrille Dray, Jacques-Olivier Klein

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2002

A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology.

Cyrille Dray, Philippe Gendrier

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002