Serge Pravossoudovitch
According to our database1,
Serge Pravossoudovitch
authored at least 131 papers
between 1990 and 2018.
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Bibliography
2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
2016
J. Electron. Test., 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
J. Electron. Test., 2014
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Characterization of an SRAM based particle detector for mixed-field radiation environments.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2012
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
2011
Proceedings of the 2011 IEEE International Test Conference, 2011
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
A study of path delay variations in the presence of uncorrelated power and ground supply noise.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Computers, 2010
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electron., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IET Comput. Digit. Tech., 2009
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.
J. Electron. Test., 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electron. Test., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
J. Electron. Test., 2007
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 12th European Test Symposium, 2007
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
Proceedings of the 12th European Test Symposium, 2007
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
J. Electron. Test., 2006
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
J. Electron. Test., 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
Proceedings of the IFIP VLSI-SoC 2006, 2006
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
J. Electron. Test., 2005
J. Electron. Test., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.
Proceedings of the Integrated Circuit and System Design, 2005
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization.
Proceedings of the 10th European Test Symposium, 2005
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs.
Proceedings of the 9th European Test Symposium, 2004
Proceedings of the 9th European Test Symposium, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
Proceedings of the 2004 Design, 2004
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 8th European Test Workshop, 2003
Proceedings of the 8th European Test Workshop, 2003
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
J. Electron. Test., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
2001
J. Electron. Test., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Random Adjacent Sequences: An Efficient Solution for Logic BIST.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
J. Electron. Test., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Integr., 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
J. Electron. Test., 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
1992
Proceedings of the Fifth International Conference on VLSI Design, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
1990
Proceedings of the European Design Automation Conference, 1990