Li-Chen Wang

According to our database, Li-Chen Wang authored at least 4 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack.

Li-Chen Wang, W. Li, Nirmaan Shanker, Suraj S. Cheema, Shang-Lin Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Yen-Kai Lin, Chenming Hu, Sayeef S. Salahuddin

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement.

Li-Chen Wang, Shao-Yun Fang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs.

Nirmaan Shanker, Li-Chen Wang, Suraj S. Cheema, Wenshen Li, Nilotpal Choudhury, Chenming Hu, Souvik Mahapatra, Sayeef S. Salahuddin

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020

Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET.

Ava J. Tan, Li-Chen Wang, Yu-Hung Liao, Jong-Ho Bae, Chenming Hu, Sayeef S. Salahuddin

Proceedings of the 2020 Device Research Conference, 2020