Shao-Yun Fang
Orcid: 0000-0001-6675-2676
According to our database1,
Shao-Yun Fang
authored at least 61 papers
between 2010 and 2024.
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Bibliography
2024
Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment Constraint.
Proceedings of the 2024 International Symposium on Physical Design, 2024
2023
Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Lamellar DSA-aware Detailed Routing Considering Double Patterning and Short Template Minimization.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2022
SpeedER: A Supervised Encoder-Decoder Driven Engine for Effective Resistance Estimation of Power Delivery Networks.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Microelectron. J., 2021
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Emerg. Top. Comput., 2019
Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Provably Good Max-Min-<i>m</i>-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Triple patterning lithography-aware detailed routing ensuring via layer decomposability.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
RouteNet: routability prediction for mixed-size designs using convolutional neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Guiding template-aware routing considering redundant via insertion for directed self-assembly.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the International Symposium on Physical Design, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Simultaneous flare level and flare variation minimization with dummification in EUVL.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010