Liang-Chi Chen

Orcid: 0000-0003-2579-4305

According to our database1, Liang-Chi Chen authored at least 17 papers between 1993 and 2023.

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Bibliography

2023
Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash.
IEEE Trans. Computers, November, 2023

WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories.
ACM Trans. Embed. Comput. Syst., October, 2023

Efficient Sanitization Design for LSM-based Key-Value Store over 3D MLC NAND Flash.
Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
LongPhase: an ultra-fast chromosome-scale phasing algorithm for small and large variants.
Bioinform., 2022

RNA-seq Quantification on Processing in memory Architecture: Observation and Characterization.
Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022

2020
Research on Aesthetic Perception of Artificial Intelligence Style Transfer.
Proceedings of the HCI International 2020 - Posters - 22nd International Conference, 2020

Applying Holo360 Video and Image Super-Resolution Generative Adversarial Networks to Virtual Reality Immersion.
Proceedings of the Human-Computer Interaction. Design and User Experience, 2020

2011
Transition test bring-up and diagnosis on UltraSPARC<sup>TM</sup> processors.
Proceedings of the 2011 IEEE International Test Conference, 2011

2009
Using transition test to understand timing behavior of logic circuits on UltraSPARC<sup>TM</sup> T2 family.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
Transition Test on UltraSPARC- T2 Microprocessor.
Proceedings of the 2008 IEEE International Test Conference, 2008

2002
TA-PSV - Timing Analysis for Partially Specified Vectors.
J. Electron. Test., 2002

2001
Crosstalk test generation on pseudo industrial circuits: a case study.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A New Gate Delay Model for Simultaneous Switching and Its Applications.
Proceedings of the 38th Design Automation Conference, 2001

2000
A new framework for static timing analysis, incremental timing refinement, and timing simulation.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1997
High Quality Robust Tests for Path Delay Faults.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1993
On-chip test generation for combinational circuits by LFSR modification.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


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