T. M. Mak

According to our database1, T. M. Mak authored at least 61 papers between 1998 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
High-speed I/O capabilities added to military automatic test equipment (ATE) using synthetic instruments.
IEEE Instrum. Meas. Mag., 2020

2017
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources.
ACM Trans. Design Autom. Electr. Syst., 2017

2015
Low-Cost On-Chip Clock Jitter Measurement Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
Clock Faults Induced Min and Max Delay Violations.
J. Electron. Test., 2014

Innovative practices session 3C: Solving today's test challenges.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Interposer test: Testing PCBs that have shrunk 100x.
Proceedings of the 2014 International Test Conference, 2014

2013
Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2012

New Design for Testability Approach for Clock Fault Testing.
IEEE Trans. Computers, 2012

2011
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
An industrial case study for X-canceling MISR.
Proceedings of the 2009 IEEE International Test Conference, 2009

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Jitters in high performance microprocessors.
Proceedings of the 2008 IEEE International Test Conference, 2008

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?.
IEEE Trans. Computers, 2007

The case for power with test.
IEEE Des. Test Comput., 2007

Novel Approach to Clock Fault Testing for High Performance Microprocessors.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Novel compensation scheme for local clocks of high performance microprocessors.
Proceedings of the 2007 IEEE International Test Conference, 2007

Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Design for Resilience to Soft Errors and Variations.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Infant Mortality--The Lesser Known Reliability Issue.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Sequential Element Design With Built-In Soft Error Resilience.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Test Consideration for Nanometer-Scale CMOS Circuits.
IEEE Des. Test Comput., 2006

Guest Editors' Introduction: Process Variation and Stochastic Design and Test.
IEEE Des. Test Comput., 2006

Is System in Package the Panacea for Integration?
IEEE Des. Test Comput., 2006

Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Soft Error Resilient System Design through Error Correction.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Should Logic SER be Solved at the Circuit Level?
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Test Challenges for 3D Circuits.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Simulating the Effects of Process Variations on Capacitive Crosstalk.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Can Clock Faults be Detected Through Functional Test?
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
On Silicon-Based Speed Path Identification.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Logic soft errors: a major barrier to robust platform design.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

DFT Assisted Built-In Soft Error Resilience.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Does It Mean Less Testing for Self Calibrating Design?.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

The Other Side of the Timing Equation: a Result of Clock Faults.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Limitation of structural scan delay test.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.
IEEE Trans. Computers, 2004

Testing Gbps Interfaces without a Gigahertz Tester.
IEEE Des. Test Comput., 2004

New Challenges in Delay Testing of Nanometer, Multigigahertz Designs.
IEEE Des. Test Comput., 2004

Defect and Error Tolerance in the Presence of Massive Numbers of Defects.
IEEE Des. Test Comput., 2004

Do We Need Anything More Than Single Bit Error Correction (ECC)?
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Elimination of Traditional Functional Testing of Interface Timings at Intel.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2004

Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Trends in manufacturing test methods and their implications.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Testing of Hard Faults in Simultaneous Multithreaded Processors.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A path-based methodology for post-silicon timing validation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Are Our Design for Testability Features Fault Secure?
Proceedings of the 2004 Design, 2004

On path-based learning and its applications in delay test and diagnosis.
Proceedings of the 41th Design Automation Conference, 2004

Design considerations and DFT to enable testing of digital interfaces.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Fault secureness need for next generation high performance microprocessor design for testability structures.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
Proceedings of the 40th Design Automation Conference, 2003

2002
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Crosstalk test generation on pseudo industrial circuits: a case study.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

1998
Cache RAM inductive fault analysis with fab defect modeling.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998


  Loading...