Haozhe Zhu

Orcid: 0000-0002-6412-3996

According to our database1, Haozhe Zhu authored at least 19 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
FAM-Former: Global Transformer and Feature Aggregation Module for Knee MRI Age Estimation.
IEEE Trans. Instrum. Meas., 2024

2023
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Road Defect Detection Based on Semantic Transformed Disparity Image Segmentation.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2022

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture.
IEEE Des. Test, 2020

XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
TRPN: Matrix Factorization Meets Recurrent Neural Network for Temporal Rating Prediction.
Proceedings of the Web and Big Data - Third International Joint Conference, 2019

2018
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017


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