Lijun Guan

According to our database, Lijun Guan authored at least 6 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.

Li Liu, Dele Tai, Bin Qiang, Lijun Guan, Chunyu Peng, Chenghu Dai, Licai Hao, Wenjuan Lu, Zhiting Lin, Qiang Zhao, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.

Chenghu Dai, Zihua Ren, Lijun Guan, Haitao Liu, Mengya Gao, Wenjuan Lu, Zhiyong Pang, Chunyu Peng, Xiulong Wu

Microelectron. J., February, 2024

2021

A note on scheduling on two identical machines with early work maximization.

Yiwei Jiang, Lijun Guan, Kun Zhang, Chang Liu, T. C. E. Cheng, Min Ji

Comput. Ind. Eng., 2021

2017

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.

Zhiting Lin, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, Junning Chen

IEEE J. Solid State Circuits, 2017

2016

Read/write margin enhanced 10T SRAM for low voltage application.

Chunyu Peng, Lijun Guan, Wenjuan Lu, Xiulong Wu, Xincun Ji

IEICE Electron. Express, 2016

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier.

Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen

IEICE Electron. Express, 2016