Junning Chen

According to our database, Junning Chen authored at least 27 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.

Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Junning Chen

IEEE J. Solid State Circuits, May, 2023

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.

Qiang Zhao, Hanwen Dong, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Junning Chen, Xiulong Wu

Int. J. Circuit Theory Appl., January, 2023

2022

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2022

In-Memory Multibit Multiplication Based on Bitline Shifting.

Jin Zhang, Zhiting Lin, Xiulong Wu, Zhongzhen Tong, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Hongbiao Wu, Junning Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point.

Pei Huang, Kuan-Chang Chang, Junlin Ge, Chunyu Peng, Xiulong Wu, Junning Chen, Zhiting Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Information sharing model of upstream supply chain based on embedded technology.

Junning Chen

Int. J. Inf. Commun. Technol., 2022

2021

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports.

Zhiting Lin, Zhiyong Zhu, Honglan Zhan, Chunyu Peng, Xiulong Wu, Yuan Yao, Jianchao Niu, Junning Chen

IEEE J. Solid State Circuits, 2021

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.

Zhiting Lin, Honglan Zhan, Zhongwei Chen, Chunyu Peng, Xiulong Wu, Wenjuan Lu, Qiang Zhao, Xuan Li, Junning Chen

IEEE J. Solid State Circuits, 2021

2020

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.

Qiang Zhao, Chunyu Peng, Junning Chen, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., 2020

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands.

Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2020

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield.

Zhiting Lin, Yong Wang, Chunyu Peng, Xiulong Wu, Xuan Li, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2020

Challenges and Solutions of the TFET Circuit Design.

Zhiting Lin, Panpan Chen, Le Ye, Xu Yan, Lanzhi Dong, Shuguang Zhang, Zhou Yang, Chunyu Peng, Xiulong Wu, Junning Chen

IEEE Trans. Circuits Syst., 2020

2019

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.

Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng

IEEE Trans. Very Large Scale Integr. Syst., 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.

Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.

Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

2018

Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application.

Chunyu Peng, Songsong Xiao, Wenjuan Lu, Jingbo Zhang, Xiulong Wu, Junning Chen, Zhiting Lin

IEEE Trans. Very Large Scale Integr. Syst., 2018

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.

Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng

IEICE Electron. Express, 2018

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.

Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2018

Computational insight into dengue virus NS2B-NS3 protease inhibition: A combined ligand- and structure-based approach.

Junning Chen, Hailun Jiang, Fangfei Li, Baichun Hu, Ying Wang, Mingxing Wang, Jian Wang, Mao-Sheng Cheng

Comput. Biol. Chem., 2018

2017

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.

Zhiting Lin, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, Junning Chen

IEEE J. Solid State Circuits, 2017

2016

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier.

Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen

IEICE Electron. Express, 2016

2015

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier.

Shoubiao Tan, Wenjuan Lu, Chunyu Peng, Zhengping Li, Youwu Tao, Junning Chen

Frontiers Inf. Technol. Electron. Eng., 2015

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102].

Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen

IEICE Electron. Express, 2015

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.

Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen

IEICE Electron. Express, 2015

2013

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip.

Xiulong Wu, Minghua Li, Zhiting Lin, Mengyuan Xi, Junning Chen

Sensors, 2013

2006

A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.

Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOS.

Yuehua Dai, Yuan Hu, Qi Liu, Daoming Ke, Junning Chen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006