Xiulong Wu

According to our database1, Xiulong Wu authored at least 30 papers between 2006 and 2021.

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Bibliography

2021
Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.
IEEE Trans. Circuits Syst., 2020

Challenges and Solutions of the TFET Circuit Design.
IEEE Trans. Circuits Syst., 2020

A new reading mode based on balanced pre-charging and group decoding.
IEICE Electron. Express, 2020

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.
IEICE Electron. Express, 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.
IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.
IEICE Electron. Express, 2019

High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2018
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.
IEICE Electron. Express, 2018

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.
IEICE Electron. Express, 2018

Picowatt 0.5 V supply with 3 ppm/°C CMOS voltage reference for energy harvesting system.
IEICE Electron. Express, 2018

2017
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.
IEEE J. Solid State Circuits, 2017

A radiation harden enhanced Quatro (RHEQ) SRAM cell.
IEICE Electron. Express, 2017

2016
Read/write margin enhanced 10T SRAM for low voltage application.
IEICE Electron. Express, 2016

Additive-calibration scheme for leakage compensation of low voltage SRAM.
IEICE Electron. Express, 2016

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.
Sci. China Inf. Sci., 2016

2015
Analyzing and modeling mobility for infrastructure-less communication.
J. Netw. Comput. Appl., 2015

Human dynamics in mobile social networks: A study of inter-node relationships.
Proceedings of the 12th International Conference on Fuzzy Systems and Knowledge Discovery, 2015

2013
The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip.
Sensors, 2013

2012
Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design.
Proceedings of the Seventh IEEE International Conference on Networking, 2012

2011
A 12T Subthreshold SRAM Bit-Cell for Medical Device Application.
Proceedings of the 2011 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2011

2006
A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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