Qiang Zhao

Orcid: 0000-0002-0278-5804

Affiliations:
  • Anhui University, School of Integrated Circuits, Hefei, China


According to our database1, Qiang Zhao authored at least 22 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023
Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.
Microelectron. J., November, 2023

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.
IEEE J. Solid State Circuits, May, 2023

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Design of radiation-hardened memory cell by polar design for space applications.
Microelectron. J., February, 2023

Four-branch Siamese network based on sketch-specific data augmentation for sketch recognition.
IET Image Process., February, 2023

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.
Int. J. Circuit Theory Appl., January, 2023

Radiation-hardened 14T SRAM cell by polar design for space applications.
IEICE Electron. Express, 2023

2022
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022

In-Memory Multibit Multiplication Based on Bitline Shifting.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.
Microelectron. J., 2022

Novel radiation-hardened latch design for space-radiation environments.
IEICE Electron. Express, 2022

2021
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.
IEEE J. Solid State Circuits, 2021

2020
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.
IEICE Electron. Express, 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.
IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.
IEICE Electron. Express, 2019

2018
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.
IEICE Electron. Express, 2018


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