Chunyu Peng

Orcid: 0000-0003-2408-5048

Affiliations:
  • Anhui University, Hefei, China


According to our database1, Chunyu Peng authored at least 47 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.
Microelectron. J., February, 2024

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

2023
Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.
Microelectron. J., November, 2023

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.
IEEE J. Solid State Circuits, May, 2023

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Threshold Switching Memristor-Based Voltage Regulative Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Design of radiation-hardened memory cell by polar design for space applications.
Microelectron. J., February, 2023

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design.
Microelectron. J., February, 2023

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.
Int. J. Circuit Theory Appl., January, 2023

Radiation-hardened 14T SRAM cell by polar design for space applications.
IEICE Electron. Express, 2023

MS3DAAM: Multi-scale 3-D Analytic Attention Module for Convolutional Neural Networks.
Proceedings of the Neural Information Processing - 30th International Conference, 2023

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022

In-Memory Multibit Multiplication Based on Bitline Shifting.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.
Microelectron. J., 2022

Novel radiation-hardened latch design for space-radiation environments.
IEICE Electron. Express, 2022

2021
Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports.
IEEE J. Solid State Circuits, 2021

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.
IEEE J. Solid State Circuits, 2021

2020
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Challenges and Solutions of the TFET Circuit Design.
IEEE Trans. Circuits Syst., 2020

A new reading mode based on balanced pre-charging and group decoding.
IEICE Electron. Express, 2020

2019
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.
IEICE Electron. Express, 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.
IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.
IEICE Electron. Express, 2019

A high performance radiation-hardened SRAM cell based on Quatro.
IEICE Electron. Express, 2019

2018
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.
IEICE Electron. Express, 2018

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.
IEICE Electron. Express, 2018

2017
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.
IEEE J. Solid State Circuits, 2017

A radiation harden enhanced Quatro (RHEQ) SRAM cell.
IEICE Electron. Express, 2017

2016
Read/write margin enhanced 10T SRAM for low voltage application.
IEICE Electron. Express, 2016

Additive-calibration scheme for leakage compensation of low voltage SRAM.
IEICE Electron. Express, 2016

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier.
IEICE Electron. Express, 2016

2015
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier.
Frontiers Inf. Technol. Electron. Eng., 2015

Image-to-class distance ratio: A feature filtering metric for image classification.
Neurocomputing, 2015

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102].
IEICE Electron. Express, 2015

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.
IEICE Electron. Express, 2015

Human dynamics in mobile social networks: A study of inter-node relationships.
Proceedings of the 12th International Conference on Fuzzy Systems and Knowledge Discovery, 2015


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