Lorenzo Ferretti

Orcid: 0000-0002-8935-6796

According to our database1, Lorenzo Ferretti authored at least 16 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs.
CoRR, 2024

2023
Graph Neural Networks for High-Level Synthesis Design Space Exploration.
ACM Trans. Design Autom. Electr. Syst., March, 2023

Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SAT-MapIt: An Open Source Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration.
IEEE Trans. Emerg. Top. Comput., 2021

DB4HLS: A Database of High-Level Synthesis Design Space Explorations.
IEEE Embed. Syst. Lett., 2021

A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration.
CoRR, 2021

2020
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Lattice-Traversing Design Space Exploration for High Level Synthesis.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2016
An Indoor Localization System for Telehomecare Applications.
IEEE Trans. Syst. Man Cybern. Syst., 2016


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