Giovanni Ansaloni
Orcid: 0000-0002-8940-3775
According to our database1,
Giovanni Ansaloni
authored at least 65 papers
between 2008 and 2024.
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Bibliography
2024
LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles.
CoRR, 2024
Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures.
Proceedings of the 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2024
2023
ACM Trans. Embed. Comput. Syst., October, 2023
Comput. Methods Programs Biomed., October, 2023
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning.
IEEE Trans. Computers, July, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Embed. Syst. Lett., 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).
Proceedings of the CF '21: Computing Frontiers Conference, 2021
2020
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing.
IEEE Embed. Syst. Lett., 2019
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
A partitioning strategy for exploring error-resilience in circuits: work-in-progress.
Proceedings of the International Conference on Compilers, 2018
2017
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery.
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing.
IEEE Trans. Computers, 2017
2016
IET Comput. Digit. Tech., 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
Sensors, 2014
Proceedings of the IEEE International Conference on Acoustics, 2014
Hardware/software approach for code synchronization in low-power multi-core sensor nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the Computing in Cardiology, CinC 2014, 2014
Live demonstration: ECG sensor interface in a low power SoC for wireless portable ECG monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities).
Proceedings of the 12th IEEE International Conference on Bioinformatics & Bioengineering, 2012
Proceedings of the 12th IEEE International Conference on Bioinformatics & Bioengineering, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2009
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Proceedings of the 2008 International Conference on Compilers, 2008