Luca P. Carloni

According to our database1, Luca P. Carloni authored at least 140 papers between 1997 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to system-on-chip design automation and latency-insensitive design".

Timeline

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Bibliography

2019
Securing Accelerators with Dynamic Information Flow Tracking.
CoRR, 2019

Teaching Heterogeneous Computing with System-Level Design Methods.
Proceedings of the Workshop on Computer Architecture Education, 2019

Cross-ISA machine instrumentation using fast and scalable dynamic binary translation.
Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2019

Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Runtime reconfigurable memory hierarchy in embedded scalable platforms.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Accelerators and Coherence: An SoC Perspective.
IEEE Micro, 2018

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.
ACM Trans. Embedded Comput. Syst., 2017

Accelerators for Breast Cancer Detection.
ACM Trans. Embedded Comput. Syst., 2017

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Broadening the exploration of the accelerator design space in embedded scalable platforms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Cross-ISA machine emulation for multicores.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

2016
A Probabilistic Ranking Model for Audio Stream Retrieval.
Proceedings of the 1st International Workshop on Multimedia Analysis and Retrieval for Multimodal Interaction, 2016

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration.
Proceedings of the 2016 International Conference on Supercomputing, 2016

A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

A synthesis-parameter tuning system for autonomous design-space exploration.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Invited - The case for embedded scalable platforms.
Proceedings of the 53rd Annual Design Automation Conference, 2016

On the design of scalable and reusable accelerators for big data applications.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.
Proceedings of the 2016 International Conference on Compilers, 2016

High-level synthesis of accelerators in embedded scalable platforms.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Energy-Harvesting Active Networked Tags (EnHANTs): Prototyping and Experimentation.
TOSN, 2015

From Latency-Insensitive Design to Communication-Based System-Level Design.
Proceedings of the IEEE, 2015

Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue].
Proceedings of the IEEE, 2015

LN-Annote: An Alternative Approach to Information Extraction from Emails using Locally-Customized Named-Entity Recognition.
Proceedings of the 24th International Conference on World Wide Web, 2015

An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors.
Proceedings of the Symposium on VLSI Circuits, 2015

Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platforms.
Proceedings of the 52nd Annual Design Automation Conference, 2015

An Analysis of Accelerator Coupling in Heterogeneous Architectures.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A low-cost, fast, and accurate microwave imaging system for breast cancer detection.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Microwave Imaging for Breast Cancer Detection: A COTS-Based Prototype.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

2014
Cloud-Aided Design for Distributed Embedded Systems.
IEEE Design & Test, 2014

Accelerator Memory Reuse in the Dark Silicon Era.
Computer Architecture Letters, 2014

A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

System-level memory optimization for high-level synthesis of component-based SoCs.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

An experimental investigation of occupancy-based energy-efficient control of commercial building indoor climate.
Proceedings of the 53rd IEEE Conference on Decision and Control, 2014

Photonic Network-on-Chip Design.
Integrated Circuits and Systems, Springer, ISBN: 978-1-4419-9334-2, 2014

2013
Flexible filters in stream programs.
ACM Trans. Embedded Comput. Syst., 2013

Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer.
J. Solid-State Circuits, 2013

An open framework to deploy heterogeneous wireless testbeds for Cyber-Physical Systems.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Modeling and implementation of energy neutral sensing systems.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

P-sync: A Photonically Enabled Architecture for Efficient Non-local Data Access.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

Prototyping energy harvesting active networked tags (EnHANTs).
Proceedings of the IEEE INFOCOM 2013, Turin, Italy, April 14-19, 2013, 2013

Dynamic Reconfiguration of Wireless Sensor Networks to Support Heterogeneous Applications.
Proceedings of the IEEE International Conference on Distributed Computing in Sensor Systems, 2013

Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead.
Proceedings of the Design, Automation and Test in Europe, 2013

On learning-based methods for design-space exploration with high-level synthesis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.
J. Solid-State Circuits, 2012

Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip.
Proceedings of the IEEE 25th International SOC Conference, 2012

Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm2.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Compositional system-level design exploration with planning of high-level synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A broadband embedded computing system for MapReduce utilizing Hadoop.
Proceedings of the 4th IEEE International Conference on Cloud Computing Technology and Science Proceedings, 2012

2011
Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors.
J. Parallel Distrib. Comput., 2011

A complete framework for programming event-driven, self-reconfigurable low power wireless networks.
Proceedings of the 9th International Conference on Embedded Networked Sensor Systems, 2011

Organic solar cell-equipped energy harvesting active networked tag (EnHANT) prototypes.
Proceedings of the 9th International Conference on Embedded Networked Sensor Systems, 2011

Demo: prototyping UWB-enabled enhants.
Proceedings of the 9th International Conference on Mobile Systems, 2011

Synthesis of Distributed Execution Platforms for Cyber-Physical Systems with Applications to High-Performance Buildings.
Proceedings of the 2011 IEEE/ACM International Conference on Cyber-Physical Systems, 2011

A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Embedded Processor Virtualization for Broadband Grid Computing.
Proceedings of the 12th IEEE/ACM International Conference on Grid Computing, 2011

VANDAL: A tool for the design specification of nanophotonic networks.
Proceedings of the Design, Automation and Test in Europe, 2011

Supervised design space exploration by compositional approximation of Pareto sets.
Proceedings of the 48th Design Automation Conference, 2011

An integrated four-phase buck converter delivering 1A/mm2 with 700ps controller delay and network-on-chip load in 45-nm SOI.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Accurate Predictive Interconnect Modeling for System-Level Design.
IEEE Trans. VLSI Syst., 2010

The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing.
Proceedings of the Conference on High Performance Computing Networking, 2010

Message from the chairs.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Silicon Nanophotonic Network-on-Chip Using TDM Arbitration.
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010

Exploiting local logic structures to optimize multi-core SoC floorplanning.
Proceedings of the Design, Automation and Test in Europe, 2010

Recursion-driven parallel code generation for multi-core platforms.
Proceedings of the Design, Automation and Test in Europe, 2010

PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks.
Proceedings of the Design, Automation and Test in Europe, 2010

Virtual channels vs. multiple physical networks: a comparative analysis.
Proceedings of the 47th Design Automation Conference, 2010

A heterogeneous parallel system running open mpi on a broadband network of embedded set-top devices.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
A Methodology for Constraint-Driven Synthesis of On-Chip Communications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Photonic NoCs: System-Level Design Exploration.
IEEE Micro, 2009

Analysis of photonic networks for a chip multiprocessor using scientific applications.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

CTC: An end-to-end flow control protocol for multi-core systems-on-chip.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Flexible filters: load balancing through backpressure for stream programs.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

A case study in distributed deployment of embedded software for camera networks.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Composing heterogeneous reactive systems.
ACM Trans. Embedded Comput. Syst., 2008

Fault-Tolerant Distributed Deployment of Embedded Control Software.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.
IEEE Trans. Computers, 2008

COSI: A Framework for the Design of Interconnection Networks.
IEEE Design & Test of Computers, 2008

Photonic networks-on-chip: Opportunities and challenges.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

Distributed flit-buffer flow control for networks-on-chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Interconnect modeling for improved system-level design optimization.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
On the Design of a Photonic Network-on-Chip.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Using functional independence conditions to optimize the performance of latency-insensitive systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Photonic NoC for DMA Communications in Chip Multiprocessors.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

A communication synthesis infrastructure for heterogeneous networked control systems and its application to building automation and control.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

The Case for Low-Power Photonic Networks on Chip.
Proceedings of the 44th Design Automation Conference, 2007

Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System.
Proceedings of the 44th Design Automation Conference, 2007

2006
Platform based design for wireless sensor networks.
MONET, 2006

Languages and Tools for Hybrid Systems Design.
Foundations and Trends in Electronic Design Automation, 2006

A Framework for Modeling the Distributed Deployment of Synchronous Designs.
Formal Methods in System Design, 2006

The Role of Back-Pressure in Implementing Latency-Insensitive Systems.
Electr. Notes Theor. Comput. Sci., 2006

Interchange Format for Hybrid Systems: Abstract Semantics.
Proceedings of the Hybrid Systems: Computation and Control, 9th International Workshop, 2006

Communication by sampling in time-sensitive distributed systems.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

Platform-based design of wireless sensor networks for industrial applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Platform-Based Design for Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

Interchange Formats for Hybrid Systems: Review and Proposal.
Proceedings of the Hybrid Systems: Computation and Control, 8th International Workshop, 2005

Rialto: a bridge between description and implementation of control algorithms for wireless sensor networks.
Proceedings of the EMSOFT 2005, 2005

Tag machines.
Proceedings of the EMSOFT 2005, 2005

Platform-Based and Derivative Design.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Heterogeneous reactive systems modeling: capturing causality and the correctness of loosely time-triggered architectures (LTTA).
Proceedings of the EMSOFT 2004, 2004

Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications.
Proceedings of the 2004 Design, 2004

Benefits and challenges for platform-based design.
Proceedings of the 41th Design Automation Conference, 2004

2003
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Efficient Synthesis of Networks On Chip.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Causality and Scheduling Constraints in Heterogeneous Reactive Systems Modeling.
Proceedings of the Formal Methods for Components and Objects, 2003

Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment.
Proceedings of the Embedded Software, Third International Conference, 2003

On-chip communication design: roadblocks and avenues.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Coping with Latency in SOC Design.
IEEE Micro, 2002

Constraint-driven communication synthesis.
Proceedings of the 39th Design Automation Conference, 2002

2001
Theory of latency-insensitive design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Modeling of Substrate Noise Injected by Digital Libraries.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Negative thinking in branch-and-bound: the case of unate covering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Performance analysis and optimization of latency insensitive systems.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Modeling digital substrate noise injection in mixed-signal IC's.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.
Proceedings of the VLSI: Systems on a Chip, 1999

A methodology for correct-by-construction latency insensitive design.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Latency Insensitive Protocols.
Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques.
IEEE Trans. Computers, 1998

1997
Negative thinking by incremental problem solving: application to unate covering.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Trace driven logic synthesis - application to power minimization.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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