Luca P. Carloni
Orcid: 0000-0001-5600-8931Affiliations:
- Columbia University, New York City, USA
According to our database1,
Luca P. Carloni
authored at least 180 papers
between 1997 and 2024.
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Bibliography
2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Des. Test, December, 2023
SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip.
ACM Trans. Embed. Comput. Syst., October, 2023
A Wireless, Mechanically Flexible, 25μm-Thick, 65, 536-Channel Subdural Surface Recording and Stimulating Microelectrode Array with Integrated Antennas.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain-Computer Interfaces.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators.
Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, 2023
DECADES: A 67mm<sup>2</sup>, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs.
Proceedings of the International Conference on Compilers, 2022
2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
IEEE Embed. Syst. Lett., 2021
hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices.
CoRR, 2021
Proceedings of the 42nd IEEE Symposium on Security and Privacy, 2021
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.
Proceedings of the Formal Methods in Computer Aided Design, 2021
2020
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Proceedings of the Workshop on Computer Architecture Education, 2019
Cross-ISA machine instrumentation using fast and scalable dynamic binary translation.
Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2019
Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019
A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.
ACM Trans. Embed. Comput. Syst., 2017
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Broadening the exploration of the accelerator design space in embedded scalable platforms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017
2016
Proceedings of the 1st International Workshop on Multimedia Analysis and Retrieval for Multimodal Interaction, 2016
Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration.
Proceedings of the 2016 International Conference on Supercomputing, 2016
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.
Proceedings of the 2016 International Conference on Compilers, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
ACM Trans. Sens. Networks, 2015
Proc. IEEE, 2015
Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue].
Proc. IEEE, 2015
LN-Annote: An Alternative Approach to Information Extraction from Emails using Locally-Customized Named-Entity Recognition.
Proceedings of the 24th International Conference on World Wide Web, 2015
An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors.
Proceedings of the Symposium on VLSI Circuits, 2015
Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platforms.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015
2014
A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
An experimental investigation of occupancy-based energy-efficient control of commercial building indoor climate.
Proceedings of the 53rd IEEE Conference on Decision and Control, 2014
Integrated Circuits and Systems, Springer, ISBN: 978-1-4419-9334-2, 2014
2013
Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer.
IEEE J. Solid State Circuits, 2013
An open framework to deploy heterogeneous wireless testbeds for Cyber-Physical Systems.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Proceedings of the IEEE INFOCOM 2013, Turin, Italy, April 14-19, 2013, 2013
Dynamic Reconfiguration of Wireless Sensor Networks to Support Heterogeneous Applications.
Proceedings of the IEEE International Conference on Distributed Computing in Sensor Systems, 2013
Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.
IEEE J. Solid State Circuits, 2012
Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip.
Proceedings of the IEEE 25th International SOC Conference, 2012
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm<sup>2</sup>.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 4th IEEE International Conference on Cloud Computing Technology and Science Proceedings, 2012
2011
Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors.
J. Parallel Distributed Comput., 2011
A complete framework for programming event-driven, self-reconfigurable low power wireless networks.
Proceedings of the 9th International Conference on Embedded Networked Sensor Systems, 2011
Organic solar cell-equipped energy harvesting active networked tag (EnHANT) prototypes.
Proceedings of the 9th International Conference on Embedded Networked Sensor Systems, 2011
Proceedings of the 9th International Conference on Mobile Systems, 2011
Synthesis of Distributed Execution Platforms for Cyber-Physical Systems with Applications to High-Performance Buildings.
Proceedings of the 2011 IEEE/ACM International Conference on Cyber-Physical Systems, 2011
A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011
Proceedings of the 12th IEEE/ACM International Conference on Grid Computing, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
An integrated four-phase buck converter delivering 1A/mm<sup>2</sup> with 700ps controller delay and network-on-chip load in 45-nm SOI.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing.
Proceedings of the Conference on High Performance Computing Networking, 2010
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
A heterogeneous parallel system running open mpi on a broadband network of embedded set-top devices.
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Analysis of photonic networks for a chip multiprocessor using scientific applications.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Computers, 2008
IEEE Des. Test Comput., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007
Using functional independence conditions to optimize the performance of latency-insensitive systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007
A communication synthesis infrastructure for heterogeneous networked control systems and its application to building automation and control.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007
Proceedings of the 44th Design Automation Conference, 2007
Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System.
Proceedings of the 44th Design Automation Conference, 2007
2006
Found. Trends Electron. Des. Autom., 2006
Formal Methods Syst. Des., 2006
Proceedings of the Hybrid Systems: Computation and Control, 9th International Workshop, 2006
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the Embedded Systems Handbook., 2005
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005
Proceedings of the Hybrid Systems: Computation and Control, 8th International Workshop, 2005
Rialto: a bridge between description and implementation of control algorithms for wireless sensor networks.
Proceedings of the EMSOFT 2005, 2005
Platform-Based and Derivative Design.
Proceedings of the Industrial Information Technology Handbook, 2005
2004
Heterogeneous reactive systems modeling: capturing causality and the correctness of loosely time-triggered architectures (LTTA).
Proceedings of the EMSOFT 2004, 2004
Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications.
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the Formal Methods for Components and Objects, 2003
Proceedings of the Embedded Software, Third International Conference, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
2002
Proceedings of the 39th Design Automation Conference, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.
Proceedings of the VLSI: Systems on a Chip, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the Computer Aided Verification, 11th International Conference, 1999
1998
IEEE Trans. Computers, 1998
1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997