Lubin Xiang

According to our database, Lubin Xiang authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 28-nm 16-Kb SRAM Computing-in-Memory Macro With Dual Bitline Computing for Boolean Logic Operation and BWN MAC Operation.

Wenjuan Lu, Lubin Xiang, Ting Wang, Simin Wang, Chunyu Peng, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., May, 2026

Low-power 11-bit SAR/SS ADC design with predictive skipping technology for CMOS image sensor applications.

Bin Qiang, Lubin Xiang, Zhicun Zhang, Yujie Tang, Xin Li, Zhigang Li, Qiang Zhao, Zhiting Lin, Xiulong Wu

Microelectron. J., 2026

A fully parallel differential two step ADC for CMOS image sensor.

Bin Qiang, Lubin Xiang, Beibei Zhang, Zhigang Li, Xin Li, Qiang Zhao, Chunyu Peng, Xi Wu, Zhiting Lin

Microelectron. J., 2026

2025

High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W.

Wenjuan Lu, Lubin Xiang, Ling Wang, Chunyu Peng, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2025