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Luis Alberto Aranda

Orcid: 0000-0003-4458-9761

According to our database1, Luis Alberto Aranda authored at least 10 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

On csauthors.net:

Bibliography

2022
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Oscar Ruano
,
Francisco Garcia-Herrero
,
Juan Antonio Maestro
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
[BibTeX]
[DOI]
Oscar Ruano
,
Francisco Garcia-Herrero
,
Luis Alberto Aranda
,
Alfonso Sánchez-Macián
,
Laura Rodriguez
,
Juan Antonio Maestro
Sensors, 2021

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Oscar Ruano
,
Francisco Garcia-Herrero
,
Juan Antonio Maestro
IEEE Access, 2021

2020
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Alfonso Sánchez-Macián
,
Juan Antonio Maestro
IEEE Trans. Very Large Scale Integr. Syst., 2020

Toward a Fault-Tolerant Star Tracker for Small Satellite Applications.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Pedro Reviriego
,
Juan Antonio Maestro
IEEE Trans. Aerosp. Electron. Syst., 2020

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Francisco Garcia-Herrero
,
Luis Esteban
,
Alfonso Sánchez-Macián
,
Juan Antonio Maestro
IEEE Access, 2020

2019
Enhancing Instruction TLB Resilience to Soft Errors.
[BibTeX]
[DOI]
Alfonso Sánchez-Macián
,
Luis Alberto Aranda
,
Pedro Reviriego
,
Vahdaneh Kiani
,
Juan Antonio Maestro
IEEE Trans. Computers, 2019

Protection Scheme for Star Tracker Images.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Pedro Reviriego
,
Ricardo Gonzalez-Toral
,
Juan Antonio Maestro
IEEE Trans. Aerosp. Electron. Syst., 2019

ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Alfonso Sánchez-Macián
,
Juan Antonio Maestro
IEEE Access, 2019

2018
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection.
[BibTeX]
[DOI]
Luis Alberto Aranda
,
Pedro Reviriego
,
Juan Antonio Maestro
IEEE Trans. Circuits Syst. II Express Briefs, 2018


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