Luís Rolíndez

According to our database, Luís Rolíndez authored at least 8 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing.

Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez

J. Electron. Test., 2007

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test.

Luís Rolíndez, Salvador Mir, Jean-Louis Carbonéro, Dimitri Goguet, Nabil Chouba

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting.

Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro

J. Electron. Test., 2006

A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters.

Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.

Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

2005

A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation.

Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez

Microelectron. J., 2005

2004

A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns.

Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur

Proceedings of the 2004 Design, 2004

2003

An implementation of memory-based on-chip analogue test signal generation.

Salvador Mir, Luís Rolíndez, Christian Domigues, Libor Rufer

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003