Guillaume Prenat
Orcid: 0000-0003-4899-2101
According to our database1,
Guillaume Prenat
authored at least 44 papers
between 2004 and 2024.
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Bibliography
2024
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations.
CoRR, 2024
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI.
CoRR, 2024
CoRR, 2024
2023
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures.
ACM Trans. Embed. Comput. Syst., October, 2023
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale.
CoRR, 2023
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation.
CoRR, 2023
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses.
CoRR, 2023
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers.
IEEE Access, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories.
ACM J. Emerg. Technol. Comput. Syst., 2016
Multi-context non-volatile content addressable memory using magnetic tunnel junctions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
2014
InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
2005
A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation.
Microelectron. J., 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns.
Proceedings of the 2004 Design, 2004