Lukas Gerlach

According to our database, Lukas Gerlach authored at least 21 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Collide+Power: Leaking Inaccessible Data with Software-based Power Side Channels.

Andreas Kogler, Jonas Juffinger, Lukas Giner, Lukas Gerlach, Martin Schwarzl, Michael Schwarz, Daniel Gruss, Stefan Mangard

Proceedings of the 32nd USENIX Security Symposium, 2023

A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs.

Lukas Gerlach, Daniel Weber, Ruiyi Zhang, Michael Schwarz

Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

Reviving Meltdown 3a.

Daniel Weber, Fabian Thomas, Lukas Gerlach, Ruiyi Zhang, Michael Schwarz

Proceedings of the Computer Security - ESORICS 2023, 2023

Indirect Meltdown: Building Novel Side-Channel Attacks from Transient-Execution Attacks.

Daniel Weber, Fabian Thomas, Lukas Gerlach, Ruiyi Zhang, Michael Schwarz

Proceedings of the Computer Security - ESORICS 2023, 2023

A Rowhammer Reproduction Study Using the Blacksmith Fuzzer.

Lukas Gerlach, Fabian Thomas, Robert Pietsch, Michael Schwarz

Proceedings of the Computer Security - ESORICS 2023, 2023

2022

A Survey on Application Specific Processor Architectures for Digital Hearing Aids.

Lukas Gerlach, Guillermo Payá Vayá, Holger Blume

J. Signal Process. Syst., 2022

SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI.

Jens Karrenbauer, Simon C. Klein, Sven Schönewald, Lukas Gerlach, Meinolf Blawat, Jens Benndorf, Holger Blume

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021

KAVUAKA: A Low-Power Application-Specific Processor Architecture for Digital Hearing Aids.

Lukas Gerlach

PhD thesis, 2021

2020

Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers.

Florian Giesemann, Lukas Gerlach, Guillermo Payá Vayá

J. Signal Process. Syst., 2020

Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing Aids.

Jens Karrenbauer, Lukas Gerlach, Guillermo Payá Vayá, Holger Blume

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Issue-Slot Based Predication Encoding Technique for VLIW Processors.

Lukas Gerlach, Fabian Stuckmann, Holger Blume, Guillermo Payá Vayá

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019

DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters.

Angel Mario Castro Martinez, Lukas Gerlach, Guillermo Payá Vayá, Hynek Hermansky, Jasper Ooster, Bernd T. Meyer

Speech Commun., 2019

FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework.

Moritz Weißbrich, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz, Guillermo Payá Vayá

Integr., 2019

KAVUAKA: A Low Power Application Specific Hearing Aid Processor.

Lukas Gerlach, Guillermo Payá Vayá, Holger Blume

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2017

Using a genetic algorithm approach to reduce register file pressure during instruction scheduling.

Florian Giesemann, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, Fabian Pflug, Gabriele von Voigt

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP.

Lukas Gerlach, Guillermo Payá Vayá, Shuang Liu, Moritz Weißbrich, Holger Blume, Daniel Marquardt, Simon Doclo

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor.

Christopher Seifert, Joachim Thiemann, Lukas Gerlach, Tobias Volkmar, Guillermo Payá Vayá, Holger Blume, Steven van de Par

Proceedings of the 2017 IEEE International Conference on Multimedia and Expo, 2017

2016

Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors.

Lukas Gerlach, Guillermo Payá Vayá, Holger Blume

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

2015

An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors.

Lukas Gerlach, Guillermo Payá Vayá, Holger Blume

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design.

Rochus Nowosielski, Lukas Gerlach, Stephan Bieband, Guillermo Payá Vayá, Holger Blume

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices.

Julian Hartig, Lukas Gerlach, Guillermo Payá Vayá, Holger Blume

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014