Macarena C. Martínez-Rodríguez

According to our database1, Macarena C. Martínez-Rodríguez authored at least 19 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Online presence:

On csauthors.net:

Bibliography

2022
Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems.
Sensors, 2022

2021
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm.
ACM J. Emerg. Technol. Comput. Syst., 2021

SoK: Remote Power Analysis.
IACR Cryptol. ePrint Arch., 2021

Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

Attestation Waves: Platform Trust via Remote Power Analysis.
Proceedings of the Cryptology and Network Security - 20th International Conference, 2021

2020
Accelerating the Development of NTRU Algorithm on Embedded Systems.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2018
VLSI Design of Trusted Virtual Sensors.
Sensors, 2018

A comparative analysis of VLSI trusted virtual sensors.
Microprocess. Microsystems, 2018

2017
CMOS digital design of a trusted virtual sensor.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

2016
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.
Int. J. Circuit Theory Appl., 2016

2015
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach.
IEEE Trans. Control. Syst. Technol., 2015

Dedicated hardware IP module for fingerprint recognition.
Proceedings of the International Symposium on Consumer Electronics, 2015

Programmable ASICs for model predictive control.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

2014
Dedicated hardware IP module for extracting singular points from fingerprints.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
ASIC-in-the-loop methodology for verification of piecewise affine controllers.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Reducing bit flipping problems in SRAM physical unclonable functions for chip identification.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Design methodology for FPGA implementation of lattice piecewise-affine functions.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Circuit implementation of piecewise-affine functions based on lattice representation.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011


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