Pablo Navarro-Torrero

Orcid: 0009-0006-9360-4322

According to our database1, Pablo Navarro-Torrero authored at least 7 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Hardware-Rooted Device Identity for IoT: Integrating Silicon PUFs and DICE in RISC-V Embedded Systems.
IEEE Access, 2026

Open-Source Framework for Secure Hardware Design with Simulation-based Leakage Assessment.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

Multi-Partner Project: Quantum-Secure IoT-based Digital Manufacturing Pilot in QUBIP project.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025
A Side-Channel Protected and High-Performance Hardware Implementation for EdDSA25519.
IEEE Access, 2025

Optimizing Secure Elements Implementation Methods for a seamless Post-Quantum Transition.
Proceedings of the IEEE Symposium on Computers and Communications, 2025

2024
Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024



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