Eros Camacho-Ruiz

Orcid: 0000-0002-3177-2260

According to our database1, Eros Camacho-Ruiz authored at least 14 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024

2023
Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems.
Cryptogr., June, 2023

A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF.
Proceedings of the 19th International Conference on Synthesis, 2023

Design considerations for a CMOS 65-nm RTN-based PUF.
Proceedings of the 19th International Conference on Synthesis, 2023

A complete SHA-3 hardware library based on a high efficiency Keccak design.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems.
Sensors, 2022

Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems.
Cryptogr., 2022

On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF.
Proceedings of the 18th International Conference on Synthesis, 2022

High-level design of a novel PUF based on RTN.
Proceedings of the 18th International Conference on Synthesis, 2022

A novel Physical Unclonable Function using RTN.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm.
ACM J. Emerg. Technol. Comput. Syst., 2021

Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
Accelerating the Development of NTRU Algorithm on Embedded Systems.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020


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