Javier Castro-Ramirez
According to our database1,
Javier Castro-Ramirez
authored at least 11 papers
between 2006 and 2014.
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Bibliography
2014
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Reducing bit flipping problems in SRAM physical unclonable functions for chip identification.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2010
Optimization of clock-gating structures for low-leakage high-performance applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006