Francisco Eugenio Potestad-Ordóñez

According to our database, Francisco Eugenio Potestad-Ordóñez authored at least 17 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Analysis of EM Side-Channel Leakage on an RO-PUF and Proposed Countermeasures.

Alejandro Casado-Galán, Santiago Sánchez-Solano, Erica Tena-Sánchez, Luis F. Rojas-Muñoz, Francisco Eugenio Potestad-Ordóñez, Macarena C. Martínez-Rodríguez, Antonio J. Acosta

IEEE Trans. Dependable Secur. Comput., 2026

2025

TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF.

Alejandro Casado-Galán, J. Núñez-Martínez, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta

Proceedings of the 21st International Conference on Synthesis, 2025

Low Entropy Masking Protection Scheme for Ascon Cipher to Counteract Side-Channel Attacks.

Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Miguel Martín-González, Alejandro Casado-Galán, Antonio J. Acosta

Proceedings of the 40th Conference on Design of Circuits and Integrated Systems, 2025

2024

Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs.

Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Erica Tena-Sánchez

Sensors, March, 2024

Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Virginia Zúñiga-González, Antonio J. Acosta

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Hardware implementations, SCA/FIA attacks, and countermeasures for the ASCON AEAD cipher: a review.

Miguel Martín-González, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta

Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024

Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation.

Alejandro Casado-Galán, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta, Erica Tena-Sánchez

Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024

Cryptographic Security Through a Hardware Root of Trust.

Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2022

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Antonio J. Acosta, Carlos Jesús Jiménez-Fernández, Ricardo Chaves

IEEE Access, 2022

2021

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández

Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández

IEEE Access, 2021

2020

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.

Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández

Sensors, 2020

An Academic Approach to FPGA Design Based on a Distance Meter Circuit.

Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero

Rev. Iberoam. de Tecnol. del Aprendiz., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Ricardo Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

Vulnerability Analysis of Trivium FPGA Implementations.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Fault attack on FPGA implementations of Trivium stream cipher.

Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016