Erica Tena

Alejandro Casado-Galán

Sensors, March, 2024

Cryptographic Security Through a Hardware Root of Trust.

[BibT_eX]

[DOI]

Luis F. Rojas-Muñoz

Santiago Sánchez-Solano

Eros Camacho-Ruiz

Pablo Navarro-Torrero

Apurba Karmakar

Carlos Fernández García

Alejandro Casado-Galán

Pau Ortega-Castro

Antonio Acosta-Jiménez

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks.

[BibT_eX]

[DOI]

Virginia Zúñiga-González

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystem.

[BibT_eX]

[DOI]

Eros Camacho-Ruiz

Santiago Sánchez-Solano

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.

[BibT_eX]

[DOI]

Ricardo Chaves

IEEE Access, 2022

2021

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.

[BibT_eX]

[DOI]

José Miguel Mora-Gutierrez

Manuel Valencia-Barrero

Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.

[BibT_eX]

[DOI]

José Miguel Mora-Gutierrez

Manuel Valencia-Barrero

IEEE Access, 2021

2020

Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.

[BibT_eX]

[DOI]

Ricardo Chaves

Manuel Valencia-Barrero

Antonio Acosta-Jiménez

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2019

2018

Effect of Temperature Variation in Experimental DPA and DEMA Attacks.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

Power and Energy Issues on Lightweight Cryptography.

[BibT_eX]

[DOI]

Javier M. Mora-Merchan

J. Low Power Electron., 2017

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview.

[BibT_eX]

[DOI]

Tommaso Addabbo

Int. J. Circuit Theory Appl., 2017

2016

Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2016

Secure cryptographic hardware implementation issues for high-performance applications.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015

DPA vulnerability analysis on Trivium stream cipher using an optimized power model.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Programmable ASICs for model predictive control.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Industrial Technology, 2015

2014

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Low-Power Differential Logic Gates for DPA Resistant Circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.

[BibT_eX]

[DOI]

Erica Tena

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012

ASIC-in-the-loop methodology for verification of piecewise affine controllers.

[BibT_eX]

[DOI]

Erica Tena

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Reducing bit flipping problems in SRAM physical unclonable functions for chip identification.

[BibT_eX]

[DOI]

Susana Eiroa

Macarena Cristina Martínez-Rodríguez

Erica Tena