Erica Tena

According to our database1, Erica Tena authored at least 20 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Online presence:

On csauthors.net:

Bibliography

2021
Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices.
IEEE Trans. Emerg. Top. Comput., 2021

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.
IEEE Access, 2021

2020
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.
ACM J. Emerg. Technol. Comput. Syst., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.
Int. J. Circuit Theory Appl., 2019

2018
Effect of Temperature Variation in Experimental DPA and DEMA Attacks.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Power and Energy Issues on Lightweight Cryptography.
J. Low Power Electron., 2017

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview.
Int. J. Circuit Theory Appl., 2017

2016
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.
Int. J. Circuit Theory Appl., 2016

Secure cryptographic hardware implementation issues for high-performance applications.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
DPA vulnerability analysis on Trivium stream cipher using an optimized power model.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Programmable ASICs for model predictive control.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

2014
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Low-Power Differential Logic Gates for DPA Resistant Circuits.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
ASIC-in-the-loop methodology for verification of piecewise affine controllers.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Reducing bit flipping problems in SRAM physical unclonable functions for chip identification.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012


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