Maciej Bellos

According to our database, Maciej Bellos authored at least 13 papers between 1999 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

A core generator for arithmetic cores and testing structures with a network interface.

Dimitris Bakalis, Kostas Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos

J. Syst. Archit., 2006

2005

Τεχνικές ελέγχου ορθής λειτουργίας με έμφαση στη χαμηλή κατανάλωση ισχύος

Maciej Bellos

PhD thesis, 2005

Deterministic Test Vector Compression / Decompression Using an Embedded Processor.

Maciej Bellos, Dimitris Nikolos

Proceedings of the Dependable Computing, 2005

2004

An Efficient Test Vector Ordering Method for Low Power Testing.

Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Scan Cell Ordering for Low Power BIST.

Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Low Power Testing by Test Vector Ordering with Vector Repetition.

Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

Deterministic BIST for RNS Adders.

Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou

IEEE Trans. Computers, 2003

DV-TSE: Difference Vector Based Test Set Embedding.

Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris

Proceedings of the IFIP VLSI-SoC 2003, 2003

Low Power Test Set Embedding Based on Phase Shifters.

Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2002

Test Set Embedding Based on Phase Shifters.

Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos

Proceedings of the Dependable Computing, 2002

2001

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme.

Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou

Proceedings of the 2nd Latin American Test Workshop, 2001

1999

Path delay fault testing of Benes multistage interconnection networks.

Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.

Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos

Proceedings of the Dependable Computing, 1999