Dimitrios Kagaris

According to our database1, Dimitrios Kagaris authored at least 83 papers between 1992 and 2019.

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Bibliography

2019
Scheduling Mutual Exclusion Accesses in Equal-Length Jobs.
TOPC, 2019

Speeding up the discovery of combinations of differentially expressed genes for disease prediction and classification.
Comput. Methods Programs Biomed., 2019

2018
AUCTSP: an improved biomarker gene pair class predictor.
BMC Bioinformatics, 2018

2017
Hypervisor-Induced Negative Interference in Virtualized Multi-core Platforms: The P4080 Case.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

LFSR characteristic polynomial and phase shifter computation for two-dimensional test set generation.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2016
MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation.
IEEE Trans. Computers, 2016

2014
Classifying Performance Bottlenecks in Multi-threaded Applications.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013
A multi-index ROC-based methodology for high throughput experiments in gene discovery.
IJDMB, 2013

Maximizing the Lifetime of a Wireless Sensor Network with Fixed Targets.
Ad Hoc & Sensor Wireless Networks, 2013

2012
Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2009
An Improved Search Method for Accumulator-Based Test Set Embedding.
IEEE Trans. Computers, 2009

Minimizing Observation Points for Fault Location.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Graph Theory and Algorithms.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Deterministic Built-in TPG with Segmented FSMs.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
A Methodology for Transistor-Efficient Supergate Design.
IEEE Trans. VLSI Syst., 2007

Minimization of Linear Dependencies Through the Use of Phase Shifters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Improved TDM switching assignments for variable and fixed burst length.
Int. J. Satellite Communications Networking, 2007

Transistor-Level Synthesis for Low-Power Applications.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Cellular Automata with Large Channel Separations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

LFSR Reseeding with Irreducible Polynomials.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
Throughput performance of an adaptive ARQ scheme in Rayleigh fading channels.
IEEE Trans. Wireless Communications, 2006

On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

InTeRail: A Test Architecture for Core-Based SOCs.
IEEE Trans. Computers, 2006

Maximum sequence test pattern generators with irreducible characteristic polynomials.
Microprocessors and Microsystems, 2006

A similarity transform for linear finite state machines.
Discret. Appl. Math., 2006

Transistor-Level Optimization of Supergates.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Phase shifts and linear dependencies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Diophantine-Equation Based Arithmetic Test Set Embedding.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
A unified method for phase shifter computation.
ACM Trans. Design Autom. Electr. Syst., 2005

Phase Shifter Merging.
J. Electronic Testing, 2005

Comparative study of CA with phase shifters and GLFSRs.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004
Accumulator based Test-per-Scan BIST.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003
Multiple-Seed TPG Structures.
IEEE Trans. Computers, 2003

On minimum delay clustering without replication.
Integr., 2003

LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds.
J. Electronic Testing, 2003

Built-In TPG with Designed Phaseshifts.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

DV-TSE: Difference Vector Based Test Set Embedding.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Low Power Test Set Embedding Based on Phase Shifters.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002
On the nonenumerative path delay fault simulation problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Linear dependencies in extended LFSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.
J. Electronic Testing, 2002

Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Test Set Embedding Based on Phase Shifters.
Proceedings of the Dependable Computing, 2002

2001
Von Neumann hybrid cellular automata for generating deterministic test sequences.
ACM Trans. Design Autom. Electr. Syst., 2001

Computational analysis of counter-based schemes for VLSI test pattern generation.
Discret. Appl. Math., 2001

2000
Test-set partitioning for multi-weighted random LFSRs.
Integr., 2000

Methods for on-chip embedding of path delay test vectors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
ATPG and BIST.
Proceedings of the VLSI Handbook., 1999

On the design of optimal counter-based schemes for test set embedding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Transmissions in a network with capacities and delays.
Networks, 1999

Maximum weighted independent sets on transitive graphs and applications1.
Integr., 1999

Embedded cores using built-in mechanisms.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
On-Chip Test Embedding for Multi-Weighted Random LFSRs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

A routing algorithm for row-based FPGAs.
Microprocess. Microsystems, 1997

Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Maximum independent sets on transitive graphs and their applications in testing and CAD.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Cellular automata for generating deterministic test sequences.
Proceedings of the European Design and Test Conference, 1997

1996
A fast algorithm for minimizing FPGA combinational and sequential modules.
ACM Trans. Design Autom. Electr. Syst., 1996

On the Use of Counters for Reproducing Deterministic Test Sets.
IEEE Trans. Computers, 1996

Retiming-Based Partial Scan.
IEEE Trans. Computers, 1996

Generating deterministic unordered test patterns with counters.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

A multiseed counter TPG with performance guarantee.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Deterministic Test Pattern Reproduction by a Counter.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Pseudo-exhaustive built-in TPG for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Avoiding linear dependencies in LFSR test pattern generators.
J. Electronic Testing, 1995

On the Computation of Fast Data Transmissions in Networks with Capacities and Delays.
Proceedings of the Algorithms and Data Structures, 4th International Workshop, 1995

Quickest paths: parallelization and dynamization .
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994
A method for pseudo-exhaustive test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

A design for testability technique for test pattern generation with LFSRs.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Retiming algorithms with application to VLSI testability.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.
IEEE Trans. VLSI Syst., 1993

Pseudoexhaustive BIST for Sequential Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Partial Scan with Retiming.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992


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