Haridimos T. Vergos

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators.

[BibT_eX]

[DOI]

A. Anastasiou

Circuits Syst. Signal Process., 2015

2014

Easily verified IP watermarking.

[BibT_eX]

[DOI]

Anastasios N. Bikos

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013

Fast parallel-prefix Ling-carry adders in QCA nanotechnology.

[BibT_eX]

[DOI]

Alexios Thanos

Proceedings of the 20th IEEE International Conference on Electronics, 2013

RNS assisted image filtering and edge detection.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Digital Signal Processing, 2013

Reverse converters for RNSs with diminished-one encoded channels.

[BibT_eX]

[DOI]

Proceedings of Eurocon 2013, 2013

2012

On Modulo 2^n+1 Adder Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Area-time efficient multi-modulus adders and their applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

Area-time efficient end-around inverted carry adders.

[BibT_eX]

[DOI]

Integr., 2012

SUT-RNS Residue-to-Binary Converters Design.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Efficient modulo 2n±1 squarers.

[BibT_eX]

[DOI]

Anastasia Spyrou

Integr., 2011

On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2011

On the use of double-LSB and signed-LSB encodings for RNS.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Digital Signal Processing, 2011

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

On Implementing Efficient Modulo 2n + 1 Arithmetic Components.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2010

Fast modulo 2n+1 multi-operand adders and residue generators.

[BibT_eX]

[DOI]

Integr., 2010

A Family of Area-Time Efficient Modulo 2n+1 Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

SUT-RNS Forward and Reverse Converters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Area-Efficient Multi-moduli Squarers for RNS.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Efficient modulo 2n+1 adder architectures.

[BibT_eX]

[DOI]

Integr., 2009

Novel modulo 2n+1 subtractors.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Efficient architectures for modulo 2n-1 squares.

[BibT_eX]

[DOI]

Anastasia Spyrou

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

2008

A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Efficient modulo 2n + 1 multi-operand adders.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Design of efficient modulo 2n+1 multipliers.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

RNS multiplication/sum-of-squares units.

[BibT_eX]

[DOI]

D. Adamidis

IET Comput. Digit. Tech., 2007

An Efficient BIST Scheme for Non-Restoring Array Dividers.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

A core generator for arithmetic cores and testing structures with a network interface.

[BibT_eX]

[DOI]

J. Syst. Archit., 2006

Novel Modulo 2n + 1 Multipliers.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Efficient Diminished-1 Modulo 2^n+1 Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

On the Design of Efficient Modular Adders.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2005

KoVer: A Sophisticated Residue Arithmetic Core Generator.

[BibT_eX]

[DOI]

Nikolaos Kostaras

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

New architectures for modulo 2N - 1 adders.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Modulo 2n - 1 multiplication/sum-of-squares units.

[BibT_eX]

[DOI]

D. Adamidis

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

Fast Parallel-Prefix Modulo 2^n+1 Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Modified Booth Modulo 2n-1 Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Diminished-1 Modulo 2n + 1 Squarer Design.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

Deterministic BIST for RNS Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Modulo 2n±1 Adder Design Using Select-Prefix Blocks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

Efficient BIST schemes for RNS datapaths.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An Efficient BIST scheme for High-Speed Adders.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Efficient modulo 2n+1 tree multipliers for diminished-1 operands.

[BibT_eX]

[DOI]

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A Family of Parallel-Pre.x Modulo 2n - 1 Adders.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

Diminished-One Modulo 2n+1 Adder Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.

[BibT_eX]

[DOI]

J. Syst. Archit., 2002

Ling adders in CMOS standard cell technologies.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers.

[BibT_eX]

[DOI]

Xrysovalantis Kavousianos

G. Ph. Alexiou

VLSI Design, 2001

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme.

[BibT_eX]

Proceedings of the 2nd Latin American Test Workshop, 2001

On Accumulator-Based Bit-Serial Test Response Compaction Schemes.

[BibT_eX]

[DOI]

Xrysovalantis Kavousianos

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

On the design of modulo 2n±1 adders.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000

High-Speed Parallel-Prefix Modulo 2n-1 Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Low Power BIST for Wallace Tree-Based Fast Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Modified Booth 1's complement and modulo 2n-1 multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

On the Yield of VLSI Processors with On-Chip CPU Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Design and Analysis of On-Chip CPU Pipelined Caches.

[BibT_eX]

C. Ninos

Proceedings of the VLSI: Systems on a Chip, 1999

Path delay fault testing of Benes multistage interconnection networks.

[BibT_eX]

[DOI]

Maciej Bellos

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

On Path Delay Fault Testing of Multiplexer - Based Shifters.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.

[BibT_eX]

[DOI]

Maciej Bellos

Xrysovalantis Kavousianos

Proceedings of the Dependable Computing, 1999

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers.

[BibT_eX]

[DOI]

G. Sidiropoulos

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1996

Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Efficient fault tolerant cache memory design.

[BibT_eX]

[DOI]