Mahdi Nazemi

Orcid: 0000-0003-4731-3568

According to our database1, Mahdi Nazemi authored at least 25 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Memory-Efficient Vision Transformers: An Activation-Aware Mixed-Rank Compression Strategy.
CoRR, 2024

2023
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

Low-Precision Mixed-Computation Models for Inference on Edge.
CoRR, 2023

Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation.
CoRR, 2023

BlendNet: Design and Optimization of a Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.
CoRR, 2023

SNT: Sharpness-Minimizing Network Transformation for Fast Compression-friendly Pretraining.
CoRR, 2023

A Fast Training-Free Compression Framework for Vision Transformers.
CoRR, 2023

Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021
Therminator 2: A Fast Thermal Simulator for Portable Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Heuristics for Million-scale Two-level Logic Minimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

DNR: A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Energy-aware Scheduling of Task Graphs with Imprecise Computations and End-to-end Deadlines.
ACM Trans. Design Autom. Electr. Syst., 2020

Pre-Defined Sparsity for Low-Complexity Convolutional Neural Networks.
IEEE Trans. Computers, 2020

A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs.
CoRR, 2020

SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Energy-efficient, low-latency realization of neural networks through boolean logic minimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference.
CoRR, 2018

A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

FFT-based deep learning deployment in embedded systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2015
ThermTap: An online power analyzer and thermal simulator for Android devices.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015


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