Ghasem Pasandi
Orcid: 0000-0001-8865-9069
According to our database1,
Ghasem Pasandi
authored at least 23 papers
between 2015 and 2023.
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Bibliography
2023
2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2020
Deep-PowerX: a deep learning-based framework for low-power approximate logic synthesis.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
2019
Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Low-power data encoding/decoding for energy-efficient static random access memory design.
IET Circuits Devices Syst., 2019
kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization.
Proceedings of the International Conference on Computer-Aided Design, 2019
Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Energy-efficient, low-latency realization of neural networks through boolean logic minimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs.
IET Circuits Devices Syst., 2018
A 256kb 9T Near-Threshold SRAM With 1k Cells per Bit-Line and Enhanced Write and Read Operations.
CoRR, 2018
PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits.
CoRR, 2018
A Graph Partitioning Algorithm with Application in Synthesizing Single Flux Quantum Logic Circuits.
CoRR, 2018
CoRR, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2016
A Novel Integer-Bit Estimation Scheme in Digital Filters Based on Probabilistic Behavior of Signals in the Internal Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A novel efficient and accurate analytical method for determining the swing of internal nodes in digital filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations.
IEEE Trans. Very Large Scale Integr. Syst., 2015