Arash Fayyazi
Orcid: 0000-0002-8088-5800
According to our database1,
Arash Fayyazi
authored at least 26 papers
between 2016 and 2024.
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Bibliography
2024
Scalable Superconductor Neuron with Ternary Synaptic Connections for Ultra-Fast SNN Hardware.
CoRR, 2024
2023
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation.
CoRR, 2023
BlendNet: Design and Optimization of a Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.
CoRR, 2023
SNT: Sharpness-Minimizing Network Transformation for Fast Compression-friendly Pretraining.
CoRR, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
Have your QEC and Bandwidth too!: A lightweight cryogenic decoder for common / trivial errors, and efficient bandwidth + execution management otherwise.
CoRR, 2022
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
HIPE-MAGIC: a technology-aware synthesis and mapping flow for highly parallel execution of memristor-aided LoGIC.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors.
IEEE Internet Things J., 2018
SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application.
CoRR, 2018
2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016