Mahesh Mamidipaka

According to our database1, Mahesh Mamidipaka authored at least 8 papers between 2001 and 2004.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2004
Processor-memory coexploration using an architecture description language.
ACM Trans. Embed. Comput. Syst., 2004

IDAP: a tool for high-level power estimation of custom array structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Analytical models for leakage power estimation of memory array structures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Adaptive low-power address encoding techniques using self-organizing lists.
IEEE Trans. Very Large Scale Integr. Syst., 2003

A Methodology for Accurate Modeling of Energy Dissipation in Array Structures.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

On-chip Stack Based Memory Organization for Low Power Embedded Architectures.
Proceedings of the 2003 Design, 2003

2002
Efficient Power Reduction Techniques for Time Multiplexed Address Buses.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001
Low power address encoding using self-organizing lists.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001


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