Rathish Jayabharathi

According to our database1, Rathish Jayabharathi authored at least 13 papers between 1993 and 2016.

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Bibliography

2016
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst., 2016

2015
Non-enumerative correlation-aware path selection.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2013
Hybrid 3D pre-bonding test framework design.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Non-enumerative generation of statistical path delays for ATPG.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2006
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Exact At-speed Delay Fault Grading in Sequential Circuits.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
Proceedings of the 2005 Design, 2005

2001
DPDAT: data path direct access testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

SpeedGrade: An RTL Path Delay Fault Simulator.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1997
A Novel Solution for Chip-Level Functional Timing Verification.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1993
A Comparative Evaluation of Adders Based on Performance and Testability.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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