Maitham Shams

According to our database1, Maitham Shams authored at least 32 papers between 1996 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2018
Gate Oxide Short Defect Model in FinFETs.
J. Electron. Test., 2018

Temperature Independent Subthreshold Circuits Design.
Proceedings of the International SoC Design Conference, 2018

2017
Comprehensive investigation of gate oxide short in FinFETs.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2015
Single-ended 6T sub-threshold SRAM with horizontal local bit-lines.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2014
Investigation of Low-Voltage Pulse Parameters on Electroporation and Electrical Lysis Using a Microfluidic Device With Interdigitated Electrodes.
IEEE Trans. Biomed. Eng., 2014

2013
Analysis of Electric Fields inside Microchannels and Single Cell Electrical Lysis with a Microfluidic Device.
Micromachines, 2013

2012
A gate sizing and transistor fingering strategy for subthreshold CMOS circuits.
IEICE Electron. Express, 2012

Ultra Low Power CMOS-Based Sensor for On-Body Radiation Dose Measurements.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2011
Preference of designing CMOS subthreshold logic circuits using uniform-size transistors.
IEICE Electron. Express, 2011

A simple and effective fluidic encapsulation protocol for bioMEMS devices.
IEICE Electron. Express, 2011

2010
An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008
Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Asynchronous Adiabatic Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A symmetric mos current-mode logic universal gate for high speed applications.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer System.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Delay modeling of CMOS/CPL logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A mathematical programming approach to designing MOS current-mode logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An MCML four-bit ripple-carry adder design in 1 GHz range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
Multi-GHz energy-efficient asynchronous pipelined circuits in MOS Current Mode Logic.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Implementation of MCML universal logic gate for 10 GHz-range in 0.13 µm CMOS technology.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A unified delay model for CMOS logic styles.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

1999
A formulation for quick evaluation and optimization of digital CMOS circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Modeling and comparing CMOS implementations of the C-element.
IEEE Trans. Very Large Scale Integr. Syst., 1998

1997
Optimizing CMOS Implementations of the C-element.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


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