Manfred Schimmler

According to our database1, Manfred Schimmler
  • authored at least 64 papers between 1983 and 2017.
  • has a "Dijkstra number"2 of five.

Timeline

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Bibliography

2017
GPGPU-based identification of cointegrated portfolios.
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017

2016
Portfolio-based contract selection in commodity futures markets.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

Combining GPU and FPGA technology for efficient exhaustive interaction analysis in GWAS.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Parallelizing Epistasis Detection in GWAS on FPGA and GPU-Accelerated Computing Systems.
IEEE/ACM Trans. Comput. Biology Bioinform., 2015

High-speed exhaustive 3-locus interaction epistasis analysis on FPGAs.
J. Comput. Science, 2015

2014
An efficient implementation of PBKDF2 with RIPEMD-160 on multiple FPGAs.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

FPGA-based Acceleration of Detecting Statistical Epistasis in GWAS.
Proceedings of the International Conference on Computational Science, 2014

Quality and consistency assurance of quote data for algorithmic trading strategies.
Proceedings of the IEEE Conference on Computational Intelligence for Financial Engineering & Economics, 2014

2012
An FPGA Implementation of an Investment Strategy Processor.
Proceedings of the International Conference on Computational Science, 2012

Master/Slave assignment optimization for high performance computing in an EC2 cloud using MPI.
Network Protocols & Algorithms, 2012

Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA.
Int. J. Reconfig. Comp., 2012

Improvement of BLASTp on the FPGA-Based High-Performance Computer RIVYERA.
Proceedings of the Bioinformatics Research and Applications - 8th International Symposium, 2012

Dictionary Attack on TrueCrypt with RIVYERA S3-5000.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

2011
Massively parallel FPGA-based implementation of BLASTp with the two-hit method.
Proceedings of the International Conference on Computational Science, 2011

MPI Performance Analysis of Amazon EC2 Cloud Services for High Performance Computing.
Proceedings of the Advances in Computing and Communications, 2011

2010
Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics.
Proceedings of the International Conference on Computational Science, 2010

Collecting Statistical Information in DNA Sequences for the Detection of Special Motifs.
Proceedings of the International Conference on Bioinformatics & Computational Biology, 2010

2009
A Massively Parallel Architecture for Bioinformatics.
Proceedings of the Computational Science, 2009

2008
Massively Parallelized DNA Motif Search on the Reconfigurable Hardware Platform COPACOBANA.
Proceedings of the Pattern Recognition in Bioinformatics, 2008

Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis.
Proceedings of the FPL 2008, 2008

A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures.
Proceedings of the 2008 International Conference on Computer Design, 2008

BMA - Boolean Matrices as Model for Motif Kernels.
Proceedings of the International Conference on Bioinformatics, 2008

2007
Parallel Computing with Low-Cost FPGAs: A Framework for COPACOBANA.
Proceedings of the Parallel Computing: Architectures, 2007

2006
PLUG: An Agent Based Prototype Validation of CAD-Constructions.
Proceedings of the 2006 International Conference on Information & Knowledge Engineering, 2006

COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

A Configuration Concept for a Massively Parallel FPGA Architecture.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005
Hardware Enhanced Biosequence Alignment.
Proceedings of The 2005 International Conference on Mathematics and Engineering Techniques in Medicine and Biological Sciences, 2005

Efficient Hardware Architectures for Modular Multiplication on FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Completely Redundant Modular Exponentiation by Operand Changing.
Proceedings of the 2005 International Conference on Computer Design, 2005

2004
A bit-serial floating-point unit for a massively parallel system on a chip.
Parallel Algorithms Appl., 2004

Fast Modular Multiplication by Operand Changing.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and Time.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
An Area-Efficient Bit-Serial Integer Multiplier.
Proceedings of the International Conference on VLSI, 2003

A Simple Circuit to Reduce the Search Range for Large Prime Numbers.
Proceedings of the International Conference on VLSI, 2003

Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Efficient Parallel Multiplication Algorithm for Large Integres.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

Key Generation for Secure High Speed Communication.
Proceedings of the International Conference on Security and Management, 2003

Area and Time Efficient Modular Multiplication of Large Integers.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
A hybrid architecture for bioinformatics.
Future Generation Comp. Syst., 2002

Massively Parallel Solutions for Molecular Sequence Analysis.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Tomographic Image Reconstruction on the Instruction Systolic Array.
Computers and Artificial Intelligence, 2001

Protein Sequence Comparison on the Instruction Systolic Array.
Proceedings of the Parallel Computing Technologies, 2001

Scanning Biosequence Databases on a Hybrid Parallel Architecture.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
KPROC - An Instruction Systolic Architecture for Parallel Prefix Applications.
Scalable Computing: Practice and Experience, 2000

Architectures and Algorithms for Multimedia Applications.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
A Morphological Approach to Hough Transform on an Instruction Systolic Array.
Computers and Artificial Intelligence, 1999

A Parallel Accelerator Architecture for Multimedia Video Compression.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997
Morphological Hough Transform on the Instruction Systolic Array.
Proceedings of the Euro-Par '97 Parallel Processing, 1997

1994
The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers.
Proceedings of the High-Performance Computing and Networking, 1994

1991
Graphenalgorithmen auf gitterverbundenen Prozessorfeldern.
PhD thesis, 1991

Parallel strong orientation on a mesh connected computer.
Parallel Computing, 1991

A Fault Tolerant and High Speed Instruction Systolic Array.
VLSI, 1991

A Reconfigurable Instruction Systolic Array.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

1990
Systolic algorithm for tensor products of matrices: implementation and applications.
Parallel Computing, 1990

1989
A Correction Network for N-Sorters.
SIAM J. Comput., 1989

A simple systolic method to find all bridges of an undirected graph.
Parallel Computing, 1989

1988
The instruction systolic array and its relation to other models of parallel computers.
Parallel Computing, 1988

A Simple Systolic Method to Find all Bridges of an Undirected Graph.
Proceedings of the Graph-Theoretic Concepts in Computer Science, 1988

A Correction Network for N-Sorters.
Proceedings of the VLSI Algorithms and Architectures, 3rd Aegean Workshop on Computing, 1988

1985
Systolic Sorting on a Mesh-Connected Network.
IEEE Trans. Computers, 1985

A Method for Realistic Comparisons of Sorting Algorithms for VLSI.
FODO, 1985

1983
A Fast Sorting Algorithm for VLSI.
Proceedings of the Automata, 1983


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