Marco Siracusa

According to our database, Marco Siracusa authored at least 12 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures.

Marco Siracusa, Olivia Hsu, Víctor Soria Pardos, Joshua Randall, Arnaud Grasset, Eric Biscondi, Douglas J. Joseph, Randy Allen, Fredrik Kjolstad, Miquel Moretó Planas, Adrià Armejach

CoRR, April, 2025

2024

SpChar: Characterizing the sparse puzzle via decision trees.

Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó

J. Parallel Distributed Comput., 2024

2023

A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors.

Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022

A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model.

Marco Siracusa, Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Samuel Williams, Donatella Sciuto, Marco Domenico Santambrogio

IEEE Trans. Computers, 2022

FPGA-based HPC accelerators: An evaluation on performance and energy efficiency.

Tan Nguyen, Colin MacLean, Marco Siracusa, Douglas Doerfler, Nicholas J. Wright, Samuel Williams

Concurr. Comput. Pract. Exp., 2022

2021

Experiences Porting the SU3_Bench Microbenchmark to the Intel Arria 10 and Xilinx Alveo U280 FPGAs.

Douglas Doerfler, Farzad Fatollahi-Fard, Colin MacLean, Tan Nguyen, Samuel Williams, Nicholas J. Wright, Marco Siracusa

Proceedings of the IWOCL'21: International Workshop on OpenCL, Munich Germany, April, 2021, 2021

Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.

Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco D. Santambrogio

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs.

Alberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco D. Santambrogio

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Tensor Optimization for High-Level Synthesis Design Flows.

Marco Siracusa, Fabrizio Ferrandi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing.

Tan Nguyen, Samuel Williams, Marco Siracusa, Colin MacLean, Douglas Doerfler, Nicholas J. Wright

Proceedings of the 2020 IEEE/ACM Performance Modeling, 2020

A CAD-based methodology to optimize HLS code via the Roofline model.

Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Samuel Williams, Marco D. Santambrogio

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications.

Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio, Lorenzo Di Tucci

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019