According to our database1, Adrià Armejach authored at least 14 papers between 2009 and 2018.
Legend:Book In proceedings Article PhD thesis Other
Stencil codes on a vector length agnostic architecture.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.
Computing in Science and Engineering, 2016
MUSA: a multi-level simulation approach for next-generation HPC machines.
Proceedings of the International Conference for High Performance Computing, 2016
Implications of non-volatile memory as primary storage for database management systems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches.
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Techniques to improve performance in requester-wins hardware transactional memory.
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
Circuit design of a dual-versioning L1 data cache.
Novel SRAM bias control circuits for a low power L1 data cache.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Transactional prefetching: narrowing the window of contention in hardware transactional memory.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
Circuit design of a dual-versioning L1 data cache for optimistic concurrency.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
EazyHTM: eager-lazy hardware transactional memory.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009