Marco D. Santambrogio

Proceedings of the 2nd Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA), 2019

An FPGA-Based Computing Infrastructure Tailored to Efficiently Scaffold Genome Sequences.

[BibT_eX]

[DOI]

Alberto Zeni

Matteo Crespi

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications.

[BibT_eX]

[DOI]

Marco Siracusa

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Automated Acceleration of Dataflow-Oriented C Applications on FPGA-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

lightweight autonomous bayesian optimization of Echo-State Networks.

[BibT_eX]

[DOI]

Giuseppe Franco

Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019

Diversity and Inclusion: Buzzword or Real Value?

[BibT_eX]

[DOI]

Proceedings of the IEEE Global Engineering Education Conference, 2019

circFA: a FPGA-based circular RNA aligner.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE EMBS International Conference on Biomedical & Health Informatics, 2019

Towards an Automatic Imaging Biopsy of Non-Small Cell Lung Cancer.

[BibT_eX]

[DOI]

Eleonora D'Arnese

Guido Walter Di Donato

Proceedings of the 2019 IEEE EMBS International Conference on Biomedical & Health Informatics, 2019

Speeding Up Resting State Networks Recognition via a Hardware Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE EMBS International Conference on Biomedical & Health Informatics, 2019

2018

Toward Smart Building Design Automation: Extensible CAD Framework for Indoor Localization Systems Deployment.

[BibT_eX]

[DOI]

Andrea Cirigliano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MARC: A Resource Consumption Modeling Service for Self-Aware Autonomous Agents.

[BibT_eX]

[DOI]

ACM Trans. Auton. Adapt. Syst., 2018

Enabling power-awareness for the Xen hypervisor.

[BibT_eX]

[DOI]

SIGBED Rev., 2018

A runtime controller for openCL applications on heterogeneous system architectures.

[BibT_eX]

[DOI]

SIGBED Rev., 2018

Towards a performance-aware power capping orchestrator for the Xen hypervisor.

[BibT_eX]

[DOI]

Marco Arnaboldi

SIGBED Rev., 2018

HLS Support for Polymorphic Parallel Memories.

[BibT_eX]

[DOI]

Giulio Stramondo

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS.

[BibT_eX]

[DOI]

Giulio Stramondo

Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

EXTRA: an open platform for reconfigurable architectures.

[BibT_eX]

[DOI]

Grigorios Chrysos

Charalampos Vatsolakis

Georgios Charitopoulos

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Automating Lung Cancer Identification in PET/CT Imaging.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018

Energy Efficiency for Autonomic Scalable Systems: Research Objectives and Preliminary Results.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018

PRETZEL: Opening the Black Box of Machine Learning Prediction Serving Systems.

[BibT_eX]

[DOI]

Yunseong Lee

Byung-Gon Chun

Markus Weimer

Matteo Interlandi

Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation, 2018

On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

FIDA: A Framework to Automatically Integrate FPGA Kernels Within Data-Science Applications.

[BibT_eX]

[DOI]

Alberto Parravicini

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Introduction to RAW 2018.

[BibT_eX]

[DOI]

Diana Goehringer

Ken Eguro

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils.

[BibT_eX]

[DOI]

Enrico Reggiani

Carlo Moroni

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

A Framework with Cloud Integration for CNN Acceleration on FPGA Devices.

[BibT_eX]

[DOI]

Niccolo Raspa

Marco Bacis

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels.

[BibT_eX]

[DOI]

Francesco Peverelli

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

TiReX: Tiled Regular eXpression Matching Architecture.

[BibT_eX]

[DOI]

Alessandro Comodi

Davide Conficconi

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Robustness of Surface EMG Classifiers with Fixed-Point Decomposition on Reconfigurable Architecture.

[BibT_eX]

[DOI]

Giuseppe Franco

Pierandrea Cancian

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

DEEP-Mon: Dynamic and Energy Efficient Power Monitoring for Container-Based Infrastructures.

[BibT_eX]

[DOI]

Rolando Brondolin

Tommaso Sardelli

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

HyPPO: Hybrid Performance-Aware Power-Capping Orchestrator.

[BibT_eX]

[DOI]

Marco Arnaboldi

Rolando Brondolin

Proceedings of the 2018 IEEE International Conference on Autonomic Computing, 2018

A Scalable FPGA Design for Cloud N-Body Simulation.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

A Unified Backend for Targeting FPGAs from DSLs.

[BibT_eX]

[DOI]

Riyadh Baghdadi

Saman P. Amarasinghe

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

FPGA-based PairHMM Forward Algorithm for DNA Variant Calling.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Five-point algorithm: An efficient cloud-based FPGA implementation.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation.

[BibT_eX]

[DOI]

Gianluca Carlo Durelli

John Lillis

IEEE Trans. Very Large Scale Integr. Syst., 2017

Power Consumption Models for Multi-Tenant Server Infrastructures.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

HUGenomics: A support to personalized medicine research.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Forum on Research and Technologies for Society and Industry, 2017

A fog-computing architecture for preventive healthcare and assisted living in smart ambients.

[BibT_eX]

[DOI]

Matteo GrecoLuca Paccanit

Sara Notargiacomo

Proceedings of the 3rd IEEE International Forum on Research and Technologies for Society and Industry, 2017

A wearable device for blind people to restore color perception.

[BibT_eX]

[DOI]

Riccardo Cavadini

M. I. Bracco

Proceedings of the 3rd IEEE International Forum on Research and Technologies for Society and Industry, 2017

BIE-PInCS: Brain injury evaluation with pupillometer based on infrared camera system.

[BibT_eX]

[DOI]

Filippo Bracco

Chiara Di Vece

Proceedings of the 3rd IEEE International Forum on Research and Technologies for Society and Industry, 2017

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Marco Bacis

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exploiting FPGAs from Higher Level Languages A Signal Analysis Case Study.

[BibT_eX]

[DOI]

Alberto Parravicini

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Highly Scalable and Efficient Parallel Design of N-Body Simulation on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Introduction to RAW Workshop.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Pearson Correlation Coefficient Acceleration for Modeling and Mapping of Neural Interconnections.

[BibT_eX]

[DOI]

Enrico Reggiani

Eleonora D'Arnese

Andrea Purgato

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Scalable Dataflow Implementation of Curran's Approximation Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Hardware Acceleration for Surface EMG Non-Negative Matrix Factorization.

[BibT_eX]

[DOI]

Pierandrea Cancian

Giuseppe Franco

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA.

[BibT_eX]

[DOI]

Marco Bacis

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Common Backend for Hardware Acceleration on FPGA.

[BibT_eX]

[DOI]

Riyadh Baghdadi

Saman P. Amarasinghe

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Optimizing streaming stencil time-step designs via FPGA floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

GPU-based computation for brain spatio-temporal networks definition.

[BibT_eX]

[DOI]

Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Software implementation and hardware acceleration of retinal vessel segmentation for diabetic retinopathy screening tests.

[BibT_eX]

[DOI]

Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains.

[BibT_eX]

[DOI]

Alessandro Pappalardo

Proceedings of the Euromicro Conference on Digital System Design, 2017

Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL.

[BibT_eX]

[DOI]

Kenneth O'Brien

Michaela Blott

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

An open reconfigurable research platform as stepping stone to exascale high-performance computing.

[BibT_eX]

[DOI]

Gabriel Figueiredo

Andreas Brokalakis

Michael Hübner

Tobias Becker

Alex J. W. Thom

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Reconfigurable embedded systems applications for versatile biomedical measurements.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

FPGA-based muscle synergy extraction for surface EMG gesture classification.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Interactive visualization for brain spatio-temporal networks.

[BibT_eX]

[DOI]

Andrea Purgato

Tanya Y. Berger-Wolf

Angus Graeme Forbes

Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017

An embedded Gabor-based palm vein recognition system.

[BibT_eX]

[DOI]

Pierandrea Cancian

Guido Walter Di Donato

Proceedings of the 2017 IEEE EMBS International Conference on Biomedical & Health Informatics, 2017

2016

Guest Editorial RAW 2014.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2016

A Software Cache Partitioning System for Hash-Based Caches.

[BibT_eX]

[DOI]

Davide Basilio Bartolini

ACM Trans. Archit. Code Optim., 2016

On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Autonomic thread scaling library for QoS management.

[BibT_eX]

[DOI]

SIGBED Rev., 2016

Special Issue on: Multicore and Many-core Architectures for Future Generation Embedded Systems.

[BibT_eX]

[DOI]

Houcine Hassan

Laurence T. Yang

Haibo Zhang

Future Gener. Comput. Syst., 2016

Using just-in-time code generation for transparent resource management in heterogeneous systems.

[BibT_eX]

[DOI]

Heinrich Riebler

Gavin Vaz

Christian Plessl

Ettore M. G. Trainiti

Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

Sink state analysis in multi-tenant smart buildings.

[BibT_eX]

[DOI]

Andrea Piscitello

Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

ProFAX: A hardware acceleration of a protein folding algorithm.

[BibT_eX]

[DOI]

Giulia Guidi

Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.

[BibT_eX]

[DOI]

Amit Kulkarni

Elias Vansteenkiste

Wayne Luk

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Preemption-aware planning on big-data systems.

[BibT_eX]

[DOI]

Matteo Mazzucchelli

Giovanni Matteo Fumarola

Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Hardware Design Automation of Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

On the Automation of High Level Synthesis of Convolutional Neural Networks.

[BibT_eX]

[DOI]

Andrea Solazzo

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

RAW Introduction and Committees.

[BibT_eX]

[DOI]

Diana Goehringer

Steven J. E. Wilton

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

On How to Improve FPGA-Based Systems Design Productivity via SDAccel.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs.

[BibT_eX]

[DOI]

Fabrizio Spada

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Parallel Protein Identification Using an FPGA-Based Solution.

[BibT_eX]

[DOI]

Fabiola Casasopra

Gea Bianchi

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Floor plan design and automatic nodes deployment for indoor location and monitoring systems.

[BibT_eX]

[DOI]

Andrea Cirigliano

Proceedings of the 2016 ACM International Joint Conference on Pervasive and Ubiquitous Computing and Proceedings of the 2016 ACM International Symposium on Wearable Computers, 2016

A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Workload-aware power optimization strategy for asymmetric multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Ruleset Minimization in Multi-tenant Smart Buildings.

[BibT_eX]

[DOI]

Andrea Piscitello

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

FFWD: Latency-Aware Event Stream Processing via Domain-Specific Load-Shedding Policies.

[BibT_eX]

[DOI]

Rolando Brondolin

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

DockerCap: A Software-Level Power Capping Orchestrator for Docker Containers.

[BibT_eX]

[DOI]

A. Asnaghi

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015

Guest Editorial ARC 2014.

[BibT_eX]

[DOI]

Diana Goehringer

João M. P. Cardoso

Koen Bertels

ACM Trans. Reconfigurable Technol. Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Danger-system: Exploring new ways to manage occupants safety in smart building.

[BibT_eX]

[DOI]

Andrea Piscitello

Francesco Paduano

Danny Noferi

Proceedings of the 2nd IEEE World Forum on Internet of Things, 2015

On how to efficiently accelerate brain network analysis on FPGA-based computing system.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures.

[BibT_eX]

[DOI]

Enrico A. Deiana

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework.

[BibT_eX]

[DOI]

Gabriele Pallotta

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board.

[BibT_eX]

[DOI]

George Charitopoulos

Danilo Pau

Proceedings of the Parallel Computing: On the Road to Exascale, 2015

Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach.

[BibT_eX]

[DOI]

Mahdi Badie Moradmand

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

RAW Introduction and Committees.

[BibT_eX]

[DOI]

Steven J. E. Wilton

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

An orchestrated approach to efficiently manage resources in heterogeneous system architectures.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

OpenMPower: An Open and Accessible Database About Real World Mobile Devices.

[BibT_eX]

[DOI]

Andrea Corna

Andrea Damiani

Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures.

[BibT_eX]

[DOI]

Gianluca Carlo Durelli

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices.

[BibT_eX]

[DOI]

Matteo Turri

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.

[BibT_eX]

[DOI]

George Charitopoulos

Xinyu Niu

Wayne Luk

Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

Power-awareness and smart-resource management in embedded computing systems.

[BibT_eX]

[DOI]

Josué Pagán

Marina Zapater

Mónica Vallejo

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

On how to extract breathing rate from PPG signal using wearable devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

A hardware approach to protein identification.

[BibT_eX]

[DOI]

Gea Bianchi

Fabiola Casasopra

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014

Coordination of Independent Loops in Self-Adaptive Systems.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2014

Automated Fine-Grained CPU Provisioning for Virtual Machines.

[BibT_eX]

[DOI]

Davide B. Bartolini

ACM Trans. Archit. Code Optim., 2014

A performance-aware quality of service-driven scheduler for multicore processors.

[BibT_eX]

[DOI]

SIGBED Rev., 2014

R3TOS-Based Autonomous Fault-Tolerant Systems.

[BibT_eX]

[DOI]

IEEE Micro, 2014

A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE World Forum on Internet of Things, 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

A Survey on Recent Hardware and Software-Level Cache Management Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

An Open-Source, Efficient, and Parameterizable Hardware Implementation of the AES Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.

[BibT_eX]

[DOI]

Gavin Vaz

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

RAW Introduction and Committees.

[BibT_eX]

[DOI]

Jürgen Becker

Jim Tørresen

Ron Sass

Philip Heng Wai Leong

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Improving the security and the scalability of the AES algorithm (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming.

[BibT_eX]

[DOI]

John Lillis

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

On How to Efficiently Implement Regular Expression Matching on FPGA-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

cODA: An Open-Source Framework to Easily Design Context-Aware Android Apps.

[BibT_eX]

[DOI]

Andrea Damiani

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

On Power and Energy Consumption Modeling for Smart Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Effective Reconfigurable Design: The FASTER Approach.

[BibT_eX]

[DOI]

Georgi Nedeltchev Gaydadjiev

Tobias Becker

Andreas Brokalakis

Wayne Luk

Ioannis Papaefstathiou

Danilo Pau

Oliver Pell

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

Power Optimization in Embedded Systems via Feedback Control of Resource Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Control. Syst. Technol., 2013

Fault Tolerance Management in Cloud Computing: A System-Level Perspective.

[BibT_eX]

[DOI]

Ravi Jhawar

Vincenzo Piuri

IEEE Syst. J., 2013

Adaptive and Flexible Smartphone Power Modeling.

[BibT_eX]

[DOI]

Mob. Networks Appl., 2013

Embedded multicore systems: Architecture, performance and application.

[BibT_eX]

[DOI]

J. Morris Chang

Pao-Ann Hsiung

Microprocess. Microsystems, 2013

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms.

[BibT_eX]

[DOI]

Ivan Beretta

IEEE Des. Test, 2013

SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

A framework for effective exploitation of partial reconfiguration in dataflow computing.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

RAW Introduction.

[BibT_eX]

[DOI]

Jürgen Becker

Peter Athanas

René Cumplido

Oliver Sander

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

HERA Project's Holistic Evolutionary Framework.

[BibT_eX]

[DOI]

Davide B. Bartolini

Matteo Carminati

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

The FASTER vision for designing dynamically reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

MPower: gain back your android battery life!

[BibT_eX]

[DOI]

Andrea Cazzola

Domenico Matteo

Proceedings of the 2013 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2013

A generalized software framework for accurate and efficient management of performance goals.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Software, 2013

Morphone.OS: Context-Awareness in Everyday Life.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

The autonomic operating system research project: achievements and future directions.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Coloring the cloud for predictable performance.

[BibT_eX]

[DOI]

Proceedings of the ACM Symposium on Cloud Computing, SOCC '13, 2013

Towards a performance-as-a-service cloud.

[BibT_eX]

[DOI]

Proceedings of the ACM Symposium on Cloud Computing, SOCC '13, 2013

A2B: An integrated framework for designing heterogeneous and reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

On self-adaptive resource allocation through reinforcement learning.

[BibT_eX]

[DOI]

Piotr J. Gmytrasiewicz

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Runtime adaptation on dataflow HPC platforms.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

ThermOS: System support for dynamic thermal management of chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

On the Evolution of Hardware Circuits via Reconfigurable Architectures.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2012

Comparison of Decision-Making Strategies for Self-Optimization in Autonomic Computing Systems.

[BibT_eX]

[DOI]

Alessandro Vittorio Papadopoulos

Jacopo Panerati

ACM Trans. Auton. Adapt. Syst., 2012

Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10).

[BibT_eX]

[DOI]

Ron Sass

Int. J. Reconfigurable Comput., 2012

TaBit: A framework for task graph to bitstream generation.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Smart technologies for effective reconfiguration: The FASTER approach.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Automatic run-time manager generation for reconfigurable MPSoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A Framework for Thermal and Performance Management.

[BibT_eX]

[DOI]

Proceedings of the 2012 Workshop on Managing Systems Automatically and Dynamically, 2012

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

DGECS: Description Generator for Evolved Circuits Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

On the automatic integration of hardware accelerators into FPGA-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An open-source design and validation platform for reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.

[BibT_eX]

[DOI]

Ioannis Papaefstathiou

Oliver Pell

M. Robart

Tim Todman

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

On the Development of a Runtime Reconfigurable Multicore System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Metronome: operating system level performance management via self-adaptive computing.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

A Parallel-Serial Decimal Multiplier Architecture.

[BibT_eX]

[DOI]

Luigi Dadda

M. Pisoni

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

MPower: Towards an Adaptive Power Management System for Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011

A New Compact SD2 Positive Integer Triangular Array Division Circuit.

[BibT_eX]

[DOI]

Renato Stefanelli

IEEE Trans. Very Large Scale Integr. Syst., 2011

Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms.

[BibT_eX]

[DOI]

Federico Nava

Stefan Herbrechtsmeier

Mario Porrmann

Ulf Witkowski

Ulrich Rückert

ACM Trans. Reconfigurable Technol. Syst., 2011

GPU-accelerated Chemical Similarity Assessment for Large Scale Databases.

[BibT_eX]

[DOI]

Marco Maggioni

Jie Liang

Proceedings of the International Conference on Computational Science, 2011

Floorplacement for Partial Reconfigurable FPGA-Based Systems.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2011

ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems.

[BibT_eX]

[DOI]

Andrea Cazzaniga

Alessandra Bonetto

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Decision making in autonomic computing systems: comparison of approaches and techniques.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Autonomic Computing, 2011

Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

A high-performance parallel implementation of the Chambolle algorithm.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Evolvable systems on reconfigurable architecture via self-aware adaptive applications.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

A bird's eye view of FPGA-based Evolvable Hardware.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Placement and Floorplanning in Dynamically Reconfigurable FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

Design flows and system architectures for adaptive computing on reconfigurable platforms.

[BibT_eX]

[DOI]

Ignacio Bravo Muñoz

J. Syst. Archit., 2010

From reconfigurable architectures to self-adaptive autonomic systems.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2010

A design workflow for dynamically reconfigurable multi-FPGA systems.

[BibT_eX]

[DOI]

Alessandro Panella

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Application heartbeats for software performance and health.

[BibT_eX]

[DOI]

Jason E. Miller

Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

High level specification of embedded listeners for monitoring of Network-on-Chips.

[BibT_eX]

[DOI]

Christoph Puttmann

Mario Porrmann

Ulrich Rückert

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A direct bitstream manipulation approach for Virtex4-based evolvable systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analysis and validation of partially dynamically reconfigurable architecture based on Xilinx FPGAs.

[BibT_eX]

[DOI]

Davide Candiloro

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Wirelength driven floorplacement for FPGA-based partial reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Application heartbeats: a generic interface for specifying program performance and goals in autonomous computing environments.

[BibT_eX]

[DOI]

Jason E. Miller

Proceedings of the 7th International Conference on Autonomic Computing, 2010

Smartlocks: lock acquisition scheduling for self-aware synchronization.

[BibT_eX]

[DOI]

David Wingate

Proceedings of the 7th International Conference on Autonomic Computing, 2010

Self-Aware Adaptation in FPGA-based Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Operating system runtime management of partially dynamically reconfigurable embedded systems.

[BibT_eX]

[DOI]

Ivan Beretta

Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

A Roadmap for Autonomous Fault-Tolerant Systems.

[BibT_eX]

[DOI]

Mikel Azkarate-askasua

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Controlling software applications via resource allocation within the heartbeats framework.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE Conference on Decision and Control, 2010

Enabling technologies for self-aware adaptive systems.

[BibT_eX]

[DOI]

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009

Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Simone Corbetta

Paola Spoletini

IEEE Trans. Very Large Scale Integr. Syst., 2009

Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2009

On-line task management for a reconfigurable cryptographic architecture.

[BibT_eX]

[DOI]

Ivan Beretta

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse.

[BibT_eX]

[DOI]

Marco Maggioni

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A runtime relocation based workflow for self dynamic reconfigurable systems design.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems.

[BibT_eX]

Jens Hagemeyer

Christopher Pohl

Mario Porrmann

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.

[BibT_eX]

[DOI]

Srinivasan Murali

Luca Benini

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

An application-centered design flow for self reconfigurable systems implementation.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Reconfigurable Computing and Hardware/Software Codesign.

[BibT_eX]

[DOI]

Toomas P. Plaks

EURASIP J. Embed. Syst., 2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.

[BibT_eX]

[DOI]

Giovanni De Micheli

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

A light-weight Network-on-Chip architecture for dynamically reconfigurable systems.

[BibT_eX]

[DOI]

Simone Corbetta

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

A Reconfiguration-Aware Floorplacer for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A design flow tailored for self dynamic reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Operating system support for online partial dynamic reconfiguration management.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Design of Communication Infrastructures for Reconfigurable Systems.

[BibT_eX]

[DOI]

Alessandro Meroni

Proceedings of the Languages for Embedded Systems and their Applications, 2008

A Requirements-Driven Simulation Framework for Communication Infrastructures Design.

[BibT_eX]

[DOI]

Alessandro Meroni

Proceedings of the Forum on specification and Design Languages, 2008

A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow.

[BibT_eX]

[DOI]

Alessandro Meroni

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Generation Flow for Self-Reconfiguration Controllers Customization.

[BibT_eX]

[DOI]

Andrea Cuoccio

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

An adaptable FPGA-based System for Regular Expression Matching.

[BibT_eX]

[DOI]

Ivano Bonesana

Marco Paolieri

Proceedings of the Design, Automation and Test in Europe, 2008

The Shining embedded system design methodology based on self dynamic reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

An adaptive genetic algorithm for dynamically reconfigurable modules allocation.

[BibT_eX]

[DOI]

Chiara Sandionigi

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching.

[BibT_eX]

[DOI]

Marco Paolieri

Ivano Bonesana

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates.

[BibT_eX]

[DOI]

Matteo Giani

Proceedings of the International Symposium on System-on-Chip, 2007

Dynamic Reconfigurability in Embedded System Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

A novel SoC design methodology combining adaptive software and reconfigurable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Davide Quarta

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity.

[BibT_eX]

Matteo Giani

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs.

[BibT_eX]

Fabio Salice

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC.

[BibT_eX]

Anna Antola

Marco Castagna

Pamela Gotti

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow.

[BibT_eX]

[DOI]

Matteo Murgida

Alessandro Panella

Proceedings of the IFIP VLSI-SoC 2006, 2006

A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures.

[BibT_eX]

[DOI]

Marco Giorgetta

Paola Spoletini

Proceedings of the IFIP VLSI-SoC 2006, 2006

Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA.

[BibT_eX]

[DOI]

Antonino Tumeo

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

MorfWeb: A New Way of Living the Web Access.

[BibT_eX]

[DOI]

Christina Tziviskou

Gesualdo Le Moli

Proceedings of the 2006 International Conference on Information and Communication Technologies and Development, 2006

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Adaptive Metrics for System-Level Functional Partitioning.

[BibT_eX]

[DOI]

Giovanni Agosta

Proceedings of the Forum on specification and Design Languages, 2006

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture.

[BibT_eX]

Carlo Amicucci

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Synthesis of Object Oriented Models on Reconfigurable Hardware.

[BibT_eX]

Giovanni Agosta

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Using speculative computation and parallelizing techniques to improve scheduling of control based designs.

[BibT_eX]

[DOI]

Gianluca Palermo

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.

[BibT_eX]

[DOI]

Alberto Donato

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Operating system support for dynamically reconfigurable SoC architectures.

[BibT_eX]

[DOI]

Alberto Donato

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms.

[BibT_eX]

[DOI]

Alberto Donato

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

A Data Oriented Approach to the Design of Reconfigurable Stream Decoders.

[BibT_eX]

[DOI]

Giovanni Agosta