Marcos Hervé

According to our database1, Marcos Hervé authored at least 10 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Data compression and decompression Integrated Circuit for AC Power Quality data.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2012
Low pin count DfT technique for RFID ICs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing.
J. Parallel Distributed Comput., 2011

Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.
J. Electron. Test., 2011

2010
Concurrent test of Network-on-Chip interconnects and routers.
Proceedings of the 11th Latin American Test Workshop, 2010

2009
Diagnosis of interconnect shorts in mesh NoCs.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors.
Proceedings of the 10th Latin American Test Workshop, 2009

NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time.
Proceedings of the 10th Latin American Test Workshop, 2009

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers, 2008


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