Fernanda Lima Kastensmidt
Orcid: 0000-0001-5767-8582Affiliations:
- Federal University of Rio Grande do Sul, Porto Alegre, Brazil
According to our database1,
Fernanda Lima Kastensmidt
authored at least 182 papers
between 1999 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Evaluating the Efficiency of Software-only Techniques to Detect SEU and SET in Microprocessors.
CoRR, 2023
Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2021
J. Electron. Test., 2021
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection.
J. Electron. Test., 2019
Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs.
Proceedings of the IEEE Latin American Test Symposium, 2019
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
Comparative Analysis of Inference Errors in a Neural Network Implemented in SRAM-Based FPGA Induced by Neutron Irradiation and Fault Injection Methods.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Reliability analysis on case-study traffic sign convolutional neural network on APSoC.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Approximate TMR for selective error mitigation in FPGAs based on testability analysis.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
2017
Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment.
Microelectron. Reliab., 2017
A low-level software-based fault tolerance approach to detect SEUs in GPUs' register files.
Microelectron. Reliab., 2017
Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology.
Microelectron. Reliab., 2017
Microprocess. Microsystems, 2017
Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
SET response of FinFET-based majority voter circuits under work-function fluctuation.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors.
ACM J. Emerg. Technol. Comput. Syst., 2016
Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-core.
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
Microelectron. Reliab., 2015
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead.
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors.
J. Electron. Test., 2015
Latency Improvement with Traffic Flow Analysis in a 3D NoC under Multiple Faulty TSVs Scenario.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments.
Proceedings of the 16th Latin-American Test Symposium, 2015
Considerations on application of selective hardening based on software fault tolerance techniques.
Proceedings of the 16th Latin-American Test Symposium, 2015
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR.
Proceedings of the 16th Latin-American Test Symposium, 2015
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2014
Microelectron. Reliab., 2014
Algorithm transformation methods to reduce the overhead of software-based fault tolerance techniques.
Microelectron. Reliab., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applications.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Implementation and experimental evaluation of a CUDA core under single event effects.
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Algorithm transformation methods to reduce software-only fault tolerance techniques' overhead.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical path.
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Configurable tool to protect processors against SEE by software-based detection techniques.
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing.
J. Parallel Distributed Comput., 2011
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.
J. Low Power Electron., 2011
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.
J. Electron. Test., 2011
J. Electron. Test., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
AdNoC case-study for Mpeg4 benchmark: improving performance and saving energy with an adaptive NoC.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Evaluating the efficiency of data-flow software-based techniques to detect SEEs in microprocessors.
Proceedings of the 12th Latin American Test Workshop, 2011
Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links.
Proceedings of the 16th European Test Symposium, 2011
2010
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies.
Microelectron. Reliab., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
The limitations of software signature and basic block sizing in soft error fault coverage.
Proceedings of the 11th Latin American Test Workshop, 2010
Efficiently using data splitting and retransmission to tolerate faults in networks-on-chip interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009
NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time.
Proceedings of the 10th Latin American Test Workshop, 2009
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies.
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers, 2008
Modeling the sensitivity of CMOS circuits to radiation induced single event transients.
Microelectron. Reliab., 2008
J. Electron. Test., 2008
Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Analyzing the effects of the granularity of recomputation based techniques to cope with radiation induced soft errors.
Proceedings of the 5th Conference on Computing Frontiers, 2008
2007
Accurate and computer efficient modelling of single event transients in CMOS circuits.
IET Circuits Devices Syst., 2007
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electron. Test., 2007
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
A built-in current sensor for high speed soft errors detection robust to process and temperature variations.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Using built-in sensors to cope with long duration transient faults in future technologies.
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
SEU Effects Evaluation on a NoC Router Architecture.
Proceedings of the 7th Latin American Test Workshop, 2006
Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk.
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM.
RITA, 2005
An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories.
IEEE Des. Test Comput., 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005
Proceedings of the 2005 Design, 2005
2004
IEEE Des. Test Comput., 2004
Proceedings of the First Conference on Computing Frontiers, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
2003
ACM Trans. Design Autom. Electr. Syst., 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
2001
J. Electron. Test., 2001
2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Designing a Mask Programmable Matrix for Sequential Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999