Alexandre M. Amory

Orcid: 0000-0001-8432-3162

According to our database1, Alexandre M. Amory authored at least 75 papers between 2000 and 2024.

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Bibliography

2024
Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF.
ACM Trans. Embed. Comput. Syst., January, 2024

2023
A Comprehensive Evaluation of Convolutional Hardware Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

2022
A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Design-Time Scheduling of Periodic, Hard Real-Time Flows for NoC-based Systems.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

ORCA RT-Bench: A Reference Architecture for Real-Time Scheduling Simulators.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020
A Survey of Aging Monitors and Reconfiguration Techniques.
CoRR, 2020

Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Energy-Aware Path Planning for Autonomous Mobile Robot Navigation.
Proceedings of the Thirty-Third International Florida Artificial Intelligence Research Society Conference, 2020

Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
Unmanned Surface Vehicle Simulator with Realistic Environmental Disturbances.
Sensors, 2019

A Survey on Unmanned Surface Vehicles for Disaster Robotics: Main Challenges and Directions.
Sensors, 2019

Autonomic Computing Towards Resource Management in Embedded Mobile Robots.
Proceedings of the Latin American Robotics Symposium, 2019

Integrating an MPSoC to a Robotics Environment.
Proceedings of the Latin American Robotics Symposium, 2019

Outdoor Localization System with Augmented State Extended Kalman Filter and Radio-Frequency Received Signal Strength.
Proceedings of the 19th International Conference on Advanced Robotics, 2019

GoDonnie: A Robot Programming Language to Improve Orientation and Mobility Skills in People Who are Visually Impaired.
Proceedings of the 21st International ACM SIGACCESS Conference on Computers and Accessibility, 2019

2018
A DfT Insertion Methodology to Scannable Q-Flop Elements.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs.
IEEE Trans. Emerg. Top. Comput., 2018

Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Software-Defined Networking Architecture for NoC-based Many-Cores.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An LSSD Compliant Scan Cell for Flip-Flops.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Overseer: A Multi Robot Monitoring Infrastructure.
Proceedings of the 15th International Conference on Informatics in Control, 2018

Toward an Accurate Hydrologic Urban Flooding Simulations for Disaster Robotics.
Proceedings of the 15th International Conference on Informatics in Control, 2018

Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

On the reuse of timing resilient architecture for testing path delay faults in critical paths.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Optimized Design of an LSSD Scan Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2017

The 2017 Humanitarian Robotics and Automation Technology Challenge [Humanitarian Technology].
IEEE Robotics Autom. Mag., 2017

Simulating Rescue of Agents in Crowds During Emergency Situations.
Proceedings of the 16th Brazilian Symposium on Computer Games and Digital Entertainment, 2017

Donnie robot: Towards an accessible and educational robot for visually impaired people.
Proceedings of the 2017 Latin American Robotics Symposium (LARS) and 2017 Brazilian Symposium on Robotics (SBR), 2017

Publish-subscribe programming for a NoC-based multiprocessor system-on-chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Teaching Robot Programming Activities for Visually Impaired Students: A Systematic Review.
Proceedings of the Universal Access in Human-Computer Interaction. Human and Technological Environments, 2017

Deep Neural Networks for Handwritten Chinese Character Recognition.
Proceedings of the 2017 Brazilian Conference on Intelligent Systems, 2017

2016
A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCs.
Proceedings of the 17th Latin-American Test Symposium, 2016

A data extraction and debugging framework for large-scale MPSoCs.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Fault Classification of the Error Detection Logic in the Blade Resilient Template.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
An integrated method for implementing online fault detection in NoC-based MPSoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fault recovery protocol for distributed memory MPSoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Distributed fault diagnosis for multiple mobile robots using an agent programming language.
Proceedings of the International Conference on Advanced Robotics, 2015

2014
A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Runtime fault recovery protocol for NoC-based MPSoCs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Optimization and Analysis of Seriation Algorithm for Ordering Protein Networks.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Bioengineering, 2014

2013
An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Fault recovery communication protocol for NoC-based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Determining the test sources/sinks for NoC TAMs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluating the scalability of test buses.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Phoenix NoC: A distributed fault tolerant architecture.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Topology-agnostic fault-tolerant NoC routing method.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.
J. Parallel Distributed Comput., 2011

Multi-task dynamic mapping onto NoC-based MPSoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Evaluating energy consumption of homogeneous MPSoCs using spare tiles.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
Crosstalk Fault Tolerant NoC: Design and Evaluation.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

2008
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers, 2008

2007
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Comput. Digit. Tech., 2007

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Redefining and testing interconnect faults in Mesh NoCs.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 11th European Test Symposium, 2006

2005
A scalable test strategy for network-on-chip routers.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
Proceedings of the 2005 Design, 2005

2004
Reducing test time with processor reuse in network-on-chip based systems.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003
Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2003, 2003

2002
A Heterogeneous and Distributed Co-Simulation Environment.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Prototyping of embedded digital systems from SDL language: a case study.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits.
Proceedings of the 2nd Latin American Test Workshop, 2001

2000
Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation.
Proceedings of the 1st Latin American Test Workshop, 2000

Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000


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