Mari Yasunaga

According to our database, Mari Yasunaga authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

IEEE Access, 2024

High Throughput Datapath Design for Vision Permutator FPGA Accelerator.

Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.

Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023